2.5.6. APB slave interface operation

The APB interface is clocked by the same clock as the AHB domain clock, dmc_aclk.

To enable a clean registered interface to the external infrastructure, the APB interface always adds a wait state for all reads and writes by driving pready LOW. In the following instances a delay of more than one wait state can be generated:

The only registers that can be accessed when the DMC is not in the Config or Low-power state are the Memory Controller Status Register, to read the current state, and the Memory Controller Command Register to change state.

To guarantee no missed auto-refresh commands it is recommended that any change of dmc_mclk period, and therefore update of the refresh period, is carried out when the DMC is in the Low-power state. This is because the refresh rate is dependent on the dmc_mclk period. It is recommended that direct commands to the external memories are only written when the DMC is in the Config state and not in the Low-power state.

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