2.5.5. Memory manager operation

The major functions of the memory manager are described in:

DMC tracking and control

The memory manager tracks and controls the state of operation of the DMC. This is controlled by the dmc_aclk domain FSM and it can be traversed by writing to the dmc_memc_cmd Register. The state of this FSM can only be traversed when the DMC is idle. For example, the ready state can only be entered from the Config state when all direct commands are completed.

Issuing commands to memory

The commands that the memory manager issues to memory are:

Direct commands

These are received over the APB interface as a result of a write to the dmc_direct_cmd Register. See DMC Direct Command Register at 0x0008. They initialize the SDRAM. The only valid commands that the memory manager can handle are:

  • NOP





Refresh commands

The refresh FSM can issue commands to the arbiter to refresh the SDRAM chips. The refresh counter is clocked by the memory clock to enable the frequency of the DMC to be scaled without affecting the refresh rate. You can program the refresh rate period using the dmc_refresh_prd Register. The value of this register is the count value in dmc_mclk cycles.

When the refresh counter wraps around zero, an individual auto-refresh sequence is requested for each external chip in turn.

Programmable options

Auto Refresh Request Period, RefreshPrd, is the time period in dmc_mclk clock cycles during which the memory manager generates a request for the arbiter to generate an auto-refresh command. This request is arbitrated as another command and is not necessarily initiated immediately. See Arbiter operation.

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