2.3.5. Memory interface

The SMC supports a NAND memory interface. The NAND memory interface is composed of command, read data and write data FIFOs, plus control logic. The memory interface logic is specific to NAND. The memory interface also contains logic that controls interaction with the EBI and prevents the memory interface from issuing commands until it is granted the external bus.

See Memory interface operation for more information.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B