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Home > Functional Overview > SMC functional operation > Clocking and resets |

This section describes:

All configurations of the SMC support at least two clock domains, and have the following clock inputs:

**smc_aclk****smc_mclk0****smc_mclk0n**.

These clocks can be grouped into two clock domains:

**AHB**domain**smc_aclk**is in this domain. You can only stop the**smc_aclk**domain signals when the SMC is in low-power mode.**Memory clock**domainThe

**smc_mclk0**and**smc_mclk0n**are in this domain.**smc_mclk0n**is an inverted version of**smc_mclk0**.**smc_mclk0**is used for timing and control signals.

You can tie off the **smc_async0** and **smc_msync0** pins so that the **smc_aclk** and **smc_mclk0** clock
domains can operate synchronously or asynchronously with respect to
each other.

- Synchronous clocking
The benefit of synchronous clocking is that you can reduce the read and write latency by removing the synchronization registers between clock domains. However, because of the integer relationship of the clocks, you might not be able to get the maximum performance from the system because of constraints placed on the bus frequency by the external memory clock speed. In synchronous mode, the handshaking between the

**smc_aclk**and**smc_mclk0**domains enables synchronous operation of the two clocks at multiples of each other, that is, ratios of n:1 and 1:m.- Asynchronous clocking
The main benefit of asynchronous clocking is that you can maximize the system performance, while running the memory interface at a fixed system frequency. Additionally, in sleep-mode situations when the system is not required to do much work, you can lower the frequency to reduce power consumption.

The SMC has two reset inputs:

- hresetn
This is the reset signal for the

**smc_aclk**domain.- smc_mreset0n
This is the reset signal for the

**smc_mclk0**domain.

You can change both reset signals asynchronously to their
respective clock domain. Internally to the SMC the deassertion of
the **hresetn **signal is synchronized
to **smc_aclk**. The deassertion
of **smc_mreset0n** is synchronized
internally to smc_mclk0 and **smc_mclk0n**.