2.1.5. Low-power interface

The memory controller has a low-power interface for each clock domain. These operate with a simple three signal protocol. It is expected that a system clock controller drives these interfaces and associated clocks. Each domain has individual control that enables one memory clock domain or all clock domains to be powered down.

See Low-power interface operation for more information.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B