2.6.1. Operating states

The operation of the SMC is based on three operating states. In this section, each state is described. Figure 2.29 shows the state machine.

Figure 2.29. smc_aclk domain FSM diagram

The SMC states are as follows:

Reset

Power is applied to the device, and hresetn is held LOW.

Ready

Normal operation of the device. You can access the SMC register bank through the AHB configuration port and external memory devices accessed through the SMC interface.

Low-power

The device does not accept new AHB transfers, and you can only access certain registers through the APB interface. You can stop the SMC clocks to reduce power consumption.

The state transitions are:

Ready to Reset

When reset is asserted to the smc_aclk domain, it enters the Reset state.

Reset to Ready

When reset is deasserted to the smc_aclk domain, it enters the Ready state.

Ready to Low-power

The Low-power state is entered when the SMC next becomes idle after either:

  • The SMC receives a low-power request through the APB smc_memc_cfg_set Register

  • The SMC receives a low-power request through the SMC low-power interface.

Low-power to Ready

The SMC exits the Low-power state back to Ready when either:

  • The SMC low-power request bit is cleared in the APB smc_memc_cfg_clr Register

  • The SMC low-power interface negates the low-power request.

Low-power to Reset

When Reset is asserted to the smc_aclk reset domain, it enters the Reset state.

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