2.5.9. Initialization

Before you can use the DMC operationally to access external memory, you must:

You might not have to configure all the DMC registers because some might power-up to the correct value, see Chapter 3 Programmer’s Model. For completeness, all register values are included in Table 2.3.

Note

You might create a deadlock situation if the DMC interface is accessed before the DMC is configured to use the APB port.

Example setup

Table 2.3 lists an example DDR setup.

Table 2.3. Example DDR setup

Register addressWrite dataDescription
0x0014

0x00000004

Set cas_latency to 2

0x00180x00000001Set t_dqss to 1
0x001C0x00000002Set t_mrd to 2
0x00200x00000007Set t_ras to 7
0x00240x0000000BSet t_rc to 11
0x00280x00000015Set t_rcd to 5 and schedule_rcd to 2
0x002C0x000001F2Set t_rfc to 18 and schedule_rfc to 15
0x00300x00000015Set t_rp to 5 and schedule_rp to 2
0x00340x00000002Set t_rrd to 2
0x00380x00000003Set t_wr to 3
0x003C0x00000002Set t_wtr to 2
0x00400x00000001Set t_xp to 1
0x00440x0000000ASet t_xsr to 10
0x00480x00000014Set t_esr to 20
0x000C0x00610009Set memory configuration[1]
0x00100x00000640Set auto refresh period to be every 1600 dmc_mclk periods
0x02000x000000FFSet chip select for chip 0 to be 0x00XXXXXX, rbc configuration
0x02040x000040FFSet chip select for chip 1 to be 0x40XXXXXX, rbc configuration
0x02080x000080FFSet chip select for chip 2 to be 0x80XXXXXX, rbc configuration
0x020C0x0000C0FFSet chip select for chip 3 to be 0xC0XXXXXX, rbc configuration
0x0008 0x000C0000Carry out chip0 Nop command
0x0008 0x00000000Carry out chip0 Prechargeall command
0x0008 0x00090000Extended mode register setup
0x0008 0x00080122Mode register setup
0x0008 0x00000000Precharge all
0x0008 0x00040000Carry out chip0 Autorefresh command
0x0008 0x00040000Carry out chip0 Autorefresh command
0x0008 0x00080032Carry out chip0 Mode Reg command 0x32 mapped to low add bits
0x0008 0x001C0000Carry out chip1 Nop command
0x0008 0x00100000Carry out chip1 Prechargeall command
0x0008 0x00190000Extended mode register setup
0x0008 0x00180122Mode register setup
0x0008 0x00100000Precharge all
0x0008 0x00140000Carry out chip1 Autorefresh command
0x0008 0x00140000Carry out chip1 Autorefresh command
0x0008 0x00180032Carry out chip1 Mode Reg command 0x32 mapped to low add bits
0x0008 0x002C0000Carry out chip2 Nop command
0x0008 0x00200000Carry out chip2 Prechargeall command
0x0008 0x00290000Extended mode register setup
0x0008 0x00280122Mode register setup
0x0008 0x00200000Precharge all
0x0008 0x00240000Carry out chip2 Autorefresh command
0x0008 0x00240000Carry out chip2 Autorefresh command
0x0008 0x00280032Carry out chip2 Mode Reg command 0x32 mapped to low add bits
0x0008 0x003C0000Carry out chip3 Nop command
0x0008 0x00300000Carry out chip3 Prechargeall command
0x0008 0x00390000Extended mode register setup
0x0008 0x00380122Mode register setup
0x0008 0x00300000Precharge all
0x0008 0x00340000Carry out chip3 Autorefresh command
0x0008 0x00340000Carry out chip3 Autorefresh command
0x0008 0x00380032Carry out chip3 Mode Reg command 0x32 mapped to low add bits
0x00040x00000000Change DMC state to Ready

[1] The memory is configured as follows:

  • - 9 column bits, 12 row bits

  • - precharge all bit is shared with A10

  • - power-down period of 0

  • - auto power down is disabled

  • - dynamic clock stopping is disabled

  • - memory burst size of 4.

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