2.5.8. Pad interface operation

You can replace or modify the pad interface if required for additional optimization for a particular memory type or target library or to use a hard macro.

It is important if the pad interface is modified or replaced that the relative timings of the control output signals enabled by command_en and data_cntl_en signals are maintained to ensure the timings carried out in the memory interface block are still correct at the external memory bus interface. The read_en signal is always asserted one dmc_mclk period before the expected read data. Therefore, the timing of read_en changes as CAS latency is changed using the APB interface.

When read commands are being executed, the data is clock-enabled into a FIFO clocked by dmc_mclk a set time from the command being clocked out. See Figure 2.27. This delay is dependent on the current cas_latency value programmed and the delays in the pad interface.

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