3.3.14. DMC t_rrd Register at 0x0034

The read/write dmc_t_rrd Register sets the Active bank x to Active bank y delay in memory clock cycles. It can only be read and written in the Config or Low-power state. Figure 3.19 shows the register bit assignments.

Figure 3.19. dmc_t_rrd Register bit assignments

Table 3.15 lists the register bit assignments.

Table 3.15. dmc_t_rrd Register bit assignments

Bits

Name

Function

[31:4]

-

Read undefined, write as zero

[3:0]

t_rrdSet Active bank x to Active bank y delay in memory clock cycles
Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B
Non-Confidential