3.3.16. DMC t_wtr Register at 0x003C

The read/write dmc_t_wtr Register sets the write to read delay in memory clock cycles. It can only be read and written in the Config or Low-power state. Figure 3.21 shows the register bit assignments.

Figure 3.21. dmc_t_wtr Register bit assignments

Table 3.17 lists the register bit assignments.

Table 3.17. dmc_t_wtr Register bit assignments

Bits

Name

Function

[31:3]

-

Read undefined, write as zero

[2:0]

t_wtrSet the write to read delay in memory clock cycles
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