3.5.6. SMC Set Cycles Register at 0x1014

This is the holding register for the smc_nand_cycles0_<0-1>. The write-only smc_set_cycles Register enables the time interval to be set for holding registers before being written to the memory manager specific registers. This register cannot be written to in either the Reset or Low-power states. Figure 3.40 shows the register bit assignments.

Note

Table 3.41 describes register holding, see Memory manager operation for more information.

Figure 3.40. smc_set_cycles Register bit assignments

Table 3.41 lists the register bit assignments.

Table 3.41. smc_set_cycles Register bit assignments

BitsNameFunction
[31:23]-Reserved, write as zero
[22:20]Set_t6Holding register for value to be written to the specific chip Register tRR field
[19:17]Set_t5Holding register for value to be written to the specific chip Register tAR field
[16:14]Set_t4Holding register for value to be written to the specific chip Register tCLR field
[13:11]Set_t3Holding register for value to be written to the specific chip Register tWP field
[10:8]Set_t2Holding register for value to be written to the specific chip Register tREA field
[7:4]Set_t1Holding register for value to be written to the specific chip Register tWC field
[3:0]Set_t0Holding register for value to be written to the specific chip Register tRC field
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