3.3.21. DMC chip_<0-3>_cfg Registers at 0x0200

The read/write dmc_chip_<0-3>_cfg Registers set up the external memory device configuration. See the Release Note for the number of external chips supported, and therefore the number of these registers. They span address locations 0x200-0x300. There is one register per memory device. The registers configure the base address and address decoding method. The registers can only be read and written in the Config or Low-power states.

Figure 3.26 shows the register bit assignments.

Figure 3.26. dmc_chip_<0-3>_cfg_Registers bit assignments

Table 3.22 lists the register bit assignments.

Table 3.22. dmc_chip_<0-3>_cfg Registers bit assignments

BitsNameFunction
[31:17]-Read undefined, write as zero.
[16]brc_n_rbc

Selects the memory organization as decoded from the AHB address:

b0 = row, bank, column organization

b1 = bank, row, column organization.

[15:8]address_matchComparison value for AHB address bits [31:24] to determine the chip that is selected.
[7:0]address_mask

The mask for AHB address bits [31:24] to determine the chip that is selected:

1 = corresponding address bit is to be used for comparison.

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