3.5.2. SMC Memory Interface Configuration Register at 0x1004

The read-only smc_memif_cfg Register provides information on the configuration of the memory interface. This register cannot be read in the Reset state. Figure 3.36 shows the register bit assignments.

Figure 3.36. smc_memif_cfg Register bit assignments

Table 3.37 lists the register bit assignments.

Table 3.37. smc_memif_cfg Register bit assignments

BitsNameFunction
[31:18]-Reserved, read undefined.
[17:16]exclusive_monitors

Returns the number of exclusive access monitor resources that are implemented in the SMC.

b00 = 0 monitors

b01 = 1 monitors

b10 = 2 monitors

b11 = 4 monitors.

[15:7]-Reserved, read undefined.
[6]remap0Returns the value of the smc_remap0 input.
[5:4]memory_width0

Returns the maximum width of the SMC memory data bus for interface 0:

b00 = 8 bits

b01 = 16 bits

b10 = 32 bits

b11 = Reserved.

[3:2]memory_chips0

Returns the number of different chip selects that the memory interface 0 supports:

b00 = 1 chip

b01 = 2 chips

b10 = 3 chips

b11 = 4 chips.

[1:0]memory_type0

Returns the memory interface 0 type:

b00 = reserved

b01 = SRAM

b10 = NAND

b11 = reserved.

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