3.3.6. DMC CAS Latency Register at 0x0014

The read/write dmc_cas_latency Register sets the CAS latency in memory clock cycles. It can only be read and written in the Config or Low-power state. Figure 3.11 shows the register bit assignments.

Figure 3.11. dmc_cas_latency Register bit assignments

Table 3.7 lists the register bit assignments.

Table 3.7. dmc_cas_latency Register bit assignments






Read undefined, write as zero.


cas_latencyCAS latency in memory clock cycles.

Encodes whether the CAS latency is half a memory clock cycle more than the value given in bits [3:1]:

1’b0 = Zero cycles offset to value in [3:1].

1’b1 = Half cycle offset to value in [3:1].

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