3.4. SMC Register summary

Figure 3.31 shows the SMC configuration register map.

Figure 3.31. SMC configuration register map

Figure 3.32 shows the SMC chip<0-1> configuration register map:

Figure 3.32. SMC chip configuration register map


Figure 3.32 shows the maximum number of supported chips. If you intend to use fewer, then the highest chip configuration blocks of the correct type are read back as zero.

Figure 3.33 shows the user configuration memory register map.

Figure 3.33. SMC user configuration register map

Figure 3.34 shows the SMC peripheral and PrimeCell identification configuration register map.

Figure 3.34. SMC peripheral and PrimeCell identification configuration register map

Table 3.35 lists the SMC Registers.

Table 3.35. SMC register summary


Base offset


Reset value

smc_memc_status0x1000RO0x00000000See SMC Memory Controller Status Register at 0x1000.
smc_memif_cfg0x1004RO0x00000016See SMC Memory Interface Configuration Register at 0x1004.
smc_memc_cfg_set0x1008WON/ASee SMC Set Configuration Register at 0x1008.
smc_memc_cfg_clr0x100CWON/ASee SMC Clear Configuration Register at 0x100C.
smc_direct_cmd0x1010WON/ASee SMC Direct Command Register at 0x1010.
smc_set_cycles0x1014WON/ASee SMC Set Cycles Register at 0x1014.
smc_set_opmode0x1018WON/ASee SMC Set Opmode Register at 0x1018.
smc_nand_cycles0_<0-1>0x1000 + chip configuration base addressRO0x00092AFF

See SMC NAND Cycles Registers <0-1> at 0x1100, 0x1120.

smc_opmode0_<0-1>0x1004 + chip configuration base addressRO0x00000001

See SMC Opmode Registers <0-1> at 0x1104, 0x1124.

smc_user_status0x1200RO0x00000000See SMC User Status Register at 0x1200.
smc_user_config0x1204WO-See SMC User Configuration Register at 0x1204.
smc_int_cfg0x1E00R/W0x00000000See SMC Integration Configuration Register at 0x1E00.
smc_int_inputs0x1E04RO-See SMC Integration Inputs Register at 0x1E04.
smc_int_outputs0x1E08WO-See SMC Integration Outputs Register at 0x1E08.
smc_periph_id_<0-3>0x1FE0-0x1FECROSee registersSee SMC Peripheral Identification Registers <0-3> at 0x1FE0-0x1FEC.
smc_pcell_id_<0-3>0x1FF0-0x1FFCROSee registersSee SMC PrimeCell Identification Registers <0-3> at 0x1FF0-0x1FFC.
Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B