3.5.9. SMC Opmode Registers <0-1> at 0x1104, 0x1124

There is an instance of the smc_opmode Register for each chip supported. This register is read-only and cannot be read in the Reset state.

The reset values of these registers are configuration-dependent. You can set the memory width for the chip select 0 of each memory interface with a tie off to enable booting from that chip. The reset value of memory width for all other chip selects is the configured width. You must set all other bits to 0x0, apart from address_match and address_mask. These are set by tie-offs at the top level.

Figure 3.43 shows the register bit assignments.

Figure 3.43. smc_opmode Register bit assignments

Table 3.44 lists the register bit assignments.

Table 3.44. smc_opmode Register bit assignments

BitsNameFunction
[31:30]-Reserved, read undefined.
[29:22]address_matchReturns the value of this tie-off. This is the comparison value for address bits [31:24] to determine the chip that is selected.
[21:14]address_maskReturns the value of this tie-off. This is the mask for address bits [31:24] to determine the chip that must be selected. Logic 1 indicates the bit is used for comparison.
[13:2]-Reserved, read undefined.
[1:0]mw

Determines the SMC memory data bus width:

b00 = 8 bits

b01 = 16 bits

b10 = reserved

b11 = reserved.

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