3.3.18. DMC t_xsr Register at 0x0044

The read/write dmc_t_xsr Register sets exit self-refresh command time in memory clock cycles. It can only be read and written in the Config or Low-power state. Figure 3.23 shows the register bit assignments.

Figure 3.23. dmc_t_xsr Register bit assignments

Table 3.19 lists the register bit assignments.

Table 3.19. dmc_t_xsr Register bit assignments

Bits

Name

Function

[31:8]

-

Read undefined, write as zero

[7:0]

t_xsrSet the exit self-refresh command time in memory clock cycles
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