3.3.1. DMC Memory Controller Status Register at 0x0000

The read-only dmc_memc_status Register provides information on the configuration of the DMC and also the current state of the DMC. It cannot be read in either the Reset or POR states. Figure 3.6 shows the register bit assignments.

Figure 3.6. dmc_memc_status Register bit assignments

Table 3.2 lists the register bit assignments.

Table 3.2. dmc_memc_status Register bit assignments






Read undefined.


Returns the number of exclusive access monitor resources implemented in the DMC:

b00 = 0 monitors

b01 = 1 monitor

b10 = 2 monitors

b11 = 4 monitors.

[9]memory_banksReturns the maximum number of banks that the DMC supports on each chip. This is fixed at 1’b1 = 4 banks.

Returns the number of different chip selects that the DMC supports:

b00 = 1 chip

b01 = 2 chips

b10 = 3 chips

b11 = 4 chips.


Returns the SDRAM that the DMC supports:

b000 = Reserved

b001 = DDR SDRAM

b011 = Reserved

b010 = Reserved

b1xx = Reserved.


Returns the width of the external memory:

b00 = 16-bit

b01 = 32-bit

b10 = 64-bit

b11 = Reserved.



Returns the state of the memory controller:

b00 = Config

b01 = Ready

b10 = Paused

b11 = Low-power.

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