3.3.5. DMC Refresh Period Register at 0x0010

The read/write dmc_refresh_prd Register sets the memory refresh period. It can only be read and written in the Config or Low-power state. Figure 3.10 shows the register bit assignments.

Figure 3.10. dmc_refresh_prd Register bit assignments

Table 3.6 lists the register bit assignments.

Table 3.6. dmc_refresh_prd Register bit assignments

Bits

Name

Function

[31:15]

-

Read undefined, write as zero

[14:0]

refresh_prdMemory refresh period in memory clock cycles
Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B
Non-Confidential