3.5.8. SMC NAND Cycles Registers <0-1> at 0x1100, 0x1120

There is an instance of this register for each NAND chip supported. The read-only smc_nand_cycles Register cannot be read in the Reset state. Figure 3.42 shows the register bit assignments.

Figure 3.42. smc_nand_cycles Register bit assignments

Figure 3.43Table 3.43 lists the register bit assignments.

Table 3.43. smc_nand_cycles Register bit assignments

[31:21]-Reserved, read undefined
[20:18]t_rrsmc_busy_0 to smc_re_n_0
[17:15]t_arID read time
[14:12]t_clrStatus read time
[11:9]t_wpsmc_we_n_0 assertion duration
[8:6]t_reasmc_re_n_0 assertion delay
[5:3]t_wcWrite cycle time
[2:0]t_rcRead cycle time
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