3.1. About the programmer’s model

Both the DMC and SMC have 4KB of memory allocated to each of them. The DMC memory extends from a base address of 0x0000 to a maximum address of 0x0FFF. The SMC memory extends from a base address of 0x1000 to a maximum address of 0x1FFF. Figure 3.1 shows that the register map address range is split into ten regions:

DMC and SMC configuration registers

Use these registers for the global configuration, and to control the operating state of the DMC and SMC.

DMC and SMC chip select configuration registers

These registers hold the operating parameters of each chip select.

DMC and SMC user configuration registers

These registers provide general purpose I/O for user specific applications.

DMC and SMC integration test registers

Use these registers to verify correct integration of the SMC within a system, by enabling non-AMBA ports to be set and read.

DMC and SMC PrimeCell Id registers

These registers enable the software to identify the system components.

Figure 3.1. DMC and SMC register map

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B