3.5.1. SMC Memory Controller Status Register at 0x1000

The read-only smc_memc_status Register provides information on the configuration of the SMC and also the current state of the SMC. This register cannot be read in the Reset state. Figure 3.35 shows the register bit assignments.

Figure 3.35. smc_memc_status Register bit assignments

Table 3.36 lists the register bit assignments.

Table 3.36. smc_memc_status Register bit assignments

BitsNameFunction
[31:6]-Reserved, read undefined
[5]raw_int_status0Current raw interrupt status for interface 0
[4]-Reserved, read undefined
[3]int_status0Current interrupt status for interface 0
[2]-Reserved, read undefined
[1]int_en0Status of memory interface 0 interrupt enable
[0]state

b0 indicates that the SMC is in Ready state

b1 indicates that the SMC is in Low-power state

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