3.3.20. DMC id_<0-5>_cfg Registers at 0x0100

The read/write dmc_id_<0-5>_cfg Registers are six registers that set the quality of service and span address locations 0x100-0x140. The registers can only be read and written in the Config or Low-power states.

Figure 3.25 shows the register bit assignments.

Figure 3.25. dmc_id_<0-5>_cfg Registers bit assignments

Table 3.21 lists the register bit assignments.

Table 3.21. dmc_id_<0-5>_cfg Registers bit assignments

[31:10]-Read undefined, write as zero
[9:2]qos_maxSet a maximum QoS
[1]qos_minSet a minimum QoS
[0]qos_enableEnables a QoS value to be applied to memory reads from address ID n
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