3.5.4. SMC Clear Configuration Register at 0x100C

The write-only smc_memc_cfg_clr Register enables the memory controller to be moved out of the Low-power state, and the interrupts disabled. This register cannot be written to in the Reset state. Figure 3.38 shows the register bit assignments.

Figure 3.38. smc_memc_cfg_clr Register bit assignments

Table 3.39 lists the register bit assignments.

Table 3.39. smc_memc_cfg_clr Register bit assignments

[31:3]-Reserved, write as zero.

b0 = no effect

b1 = request the SMC to exit Low-power state.

[1]-Reserved, write as zero.

b0 = no effect

b1 = interrupt disable, memory interface 0.

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