3.3.4. DMC Memory Configuration Register at 0x000C

The read/write dmc_memory_cfg Register configures the memory. It can only be read and written in the Config or Low-power state. Figure 3.9 shows the register bit assignments.

Figure 3.9. dmc_memory_cfg Register bit assignments

Table 3.5 lists the register bit assignments.

Table 3.5. dmc_memory_cfg Register bit assignments

Bits

Name

Function

[31:23]-Read undefined, write as zero.
[22:21]active_chips

Enables the refresh command generation for the number of memory chips. It is only possible to generate commands up to and including the number of chips in the configuration defined in the memc_status Register:

b00 = 1 chip

b01 = 2 chips

b10 = 3 chips

b11 = 4 chips.

[20:18]-Reserved, read undefined, write as zero.
[17:15]memory_burst

Encodes the number of data accesses that are performed to the SDRAM for each Read and Write command:

b000 = Reserved

b001 = Burst 2

b010 = Burst 4

b011 = Burst 8

b100 = Burst 16.

You must program this value into the SDRAM mode register using the direct_cmd Register at offset 0x8, and it must match it.

[14]stop_mem_clockWhen enabled, the memory clock is dynamically stopped when not performing an access to the SDRAM.
[13]auto_power_downWhen this is set, the memory interface automatically places the SDRAM into power-down state by deasserting CKE when the command FIFO has been empty for PowerDownPrd number of memory clock cycles.
[12:7]power_down_prd

Number of memory clock cycles for auto power-down of the SDRAM.

Minimum value = 1.

[6]

ap_bit

Encodes the position of the auto-precharge bit in the memory address:

b0 = address bit 10

b1 = address bit 8.

[5:3]row_bits

Encodes the number of bits of the AHB address that comprise the row address:

b000 = 11 bits

b001 = 12 bits

b010 = 13 bits

b011 = 14 bits

b100 = 15 bits

b101 = 16 bits.

The combination of row size, column size, BRC/RBC, and memory width must ensure that neither the MSB of the row address nor the MSB of the bank address exceeds address range [27:0].

[2:0]column_bits

Encodes the number of bits of the AHB address that comprise the column address:

b000 = 8 bits

b001 = 9 bits

b010 = 10 bits

b011 = 11 bits

b100 = 12 bits.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B
Non-Confidential