4.1. DMC and SMC integration test registers

Figure 4.1 shows the DMC integration test register map.

Figure 4.1. DMC integration test register map

Test registers are provided for integration testing. Table 4.1 lists the DMC integration test registers.

Table 4.1. DMC integration test register summary

Name

Base offset

Type

Reset value

Description

dmc_int_cfg0x0E00R/W0x0DMC Integration Configuration Register at 0x0E00
dmc_int_inputs0x0E04ROTie-off dependentDMC Integration Inputs Register at 0x0E04
dmc_int_outputs0x0E08WO-DMC Integration Outputs Register at 0x0E08

Figure 4.2 shows the SMC integration Test Register map.

Figure 4.2. SMC integration test register map

Table 4.2 lists the SMC integration test registers.

Table 4.2. SMC integration test register summary

Name

Base

offset

Type

Reset

value

Description
smc_int_cfg0x1E00R/W0x0SMC Integration Configuration Register at 0x1E00
smc_int_inputs0x1E04RO-SMC Integration Inputs Register at 0x1E04
smc_int_outputs0x1E08WO-SMC Integration Outputs Register at 0x1E08

This section describes:

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