4.1.4. SMC Integration Configuration Register at 0x1E00

The read/write smc_int_cfg Register selects the integration test registers. This register is only for test. This register cannot be read or written to in the Reset state.

Figure 4.6 shows the register bit assignments.

Figure 4.6. smc_int_cfg Register bit assignments

Table 4.6 lists the register bit assignments.

Table 4.6. smc_int_cfg Register bit assignments

[31:1]UndefinedReserved, read undefined, write as zero
[0]int_test_enWhen set, outputs are driven from the integration test registers and tied-off, and inputs can change for integration testing
Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B