2.2.4. Memory interface

The memory interface provides a clean and defined interface between the pad interface and the arbiter ensuring the external memory interface command protocols are met in accordance with the programmed timings in the register block. See Chapter 3 Programmer’s Model.

The only external I/Os to this block are dmc_mclk and dmc_mresetn.

The memory interface tracks and controls the state of the external memories using an FSM. See Figure 2.6.

Figure 2.6. dmc_mclk domain FSM diagram

See Table 2.4 for valid system states.

See Memory interface operation for more information.

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