2.6.6. Memory manager operation

The memory manager module is responsible for controlling the state of the SMC and the updating of chip configuration registers.

This subsection describes:

Low-power operation

The SMC accepts requests to enter the Low-power state through either the SMC low-power interface or the APB register interface.

The SMC does not enter the power-down state until it has received an idle indication from all areas of the peripheral, that is:

  • there is no valid transfer held in the Format block

  • there are no valid transfers held in the SMC interface

  • all FIFOs are empty

  • all memory interface blocks are IDLE.

When the Low-power state is entered, no new memory transfers are accepted until the SMC has been moved out of Low-power state. The SMC does not request to move out of Low-power state, and never refuses a power-down request.

Chip configuration registers

The SMC provides a mechanism for synchronizing the switching of operating modes of the SMC with that of the memory device.

The smc_set_cycles Register and smc_set_opmode Register act as holding registers for new operating parameters until the SMC detects the memory device has switched modes.

Figure 2.33 shows the memory manager containing a bank of registers for each memory chip supported by the SMC. The manager register bank consists of all the timing parameters smc_nand_cycles0_<0-1> and smc_opmode0_<0-1>, that are required for the controller to correctly time any type of access to a supported type.

The APB registers smc_set_cycles and smc_set_opmode act as holding registers, the configuration registers within the manager are only updated if the smc_direct_cmd Register indicates only a register update is taking place.

The chip configuration registers are available as read-only registers in the address map of the APB interface.

Figure 2.33. Chip configuration registers

Direct commands

The SMC enables code to be executed from the memory while simultaneously, from the software perspective, moving the same chip to a different operating mode. Because NAND devices do not have operating modes, you must only use the direct command to update the registers.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B