2.2.2. Memory manager

The memory manager tracks and controls the current state of the DMC using a Finite State Machine (FSM) as Figure 2.4 shows.

Figure 2.4. dmc_aclk domain FSM diagram

In Figure 2.4, non-state moving transitions are omitted for clarity. See Table 2.4 for valid system states.

APB commands to the Direct Command Register or the low-power interface control the state of the DMC. Figure 2.5 shows the low-power interface channel signals.

Figure 2.5. Low-power interface channel signals

The low-power interface channel enables low-power mode to be entered using discrete lines. You can tie off this interface to be inactive if it is not required.

The APB slave interface stalls the psel and penable signals using the pready signal if a previous command has not completed.

If an APB command is received that is illegal to carry out from the current state then it is ignored and the FSM stays in the current state.

The memory manager enables the APB slave interface to directly send initialization commands to the external memory SDRAM and periodically generate refresh commands for the external memory SDRAM.

See Memory manager operation for more information.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B