2.2.5. Pad interface

The pad interface provides a flip-flop for each external signal.

Figure 2.7 shows the pad interface external connections.

Figure 2.7. DMC Pad interface external connections

Pad interface to external memory devices

The pad interface block registers the relevant command signals with clocks that enable the external memory device timings to be met.

To support a PrimeCell EBI (PL220) the dmc_ap precharge bit signal is also an external signal to the DMC. Having dmc_ap separate to the address bus means that PRECHARGEALL commands to dynamic memory can be issued when the EBI has granted the external memory interface to another memory controller.

It is expected that a Delay-Locked Loop (DLL) is required to delay the dmc_dqs signals coming back from the memories with respect to the dmc_dq data bus. The standard delay for the dmc_dqs signals is a quarter clock period of dmc_mclk. The DLL is not included in the DMC.

See Pad interface operation for more information.

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0392B