2.2. DMC

Figure 2.3 shows a block diagram of the DMC.

Figure 2.3. DMC block diagram

The DMC interface processes the incoming transfers from the AHB ports. It can only add a read or write to the queue at any one time. It uses round-robin arbitration to decide between a simultaneous read or write.

The DMC uses a scheduling algorithm to determine the item in the queue to process next to maximize data bandwidth. The algorithm uses information including:

The QoS is set by a register within the DMC on a port by port basis. The QoS value indicates a required read maximum latency. A QoS timeout causes the transaction to be raised to a higher priority. You can also set the QoS to minimum for a specific port so that its transfers are serviced with a higher priority. This impacts the overall memory bandwidth because it limits the options of the scheduling algorithm.

The main blocks of the DMC are:

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