3.3.24. DMC Peripheral Identification Registers <0-3> at 0x0FE0-0x0FEC

The dmc_periph_id Registers are four 8-bit read-only registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single register that holds a 32-bit peripheral ID value. They are read by an external master to determine the device version of the DMC.

Table 3.25 lists the register bit assignments.

Table 3.25. dmc_periph_id Register bit assignments

BitsName

Description

[31:24]integration_cfgConfiguration options are peripheral-specific. See the DMC Peripheral Identification Register 3.
[23:20]-The peripheral revision number is revision dependent.
[19:12]designerDesigner’s ID number. This is 0x41 for ARM.
[11:0]

part_number

Identifies the peripheral.

The part number for the DMC is 0x340.

Figure 3.29 shows the correspondence between bits of the dmc_periph_id registers and the conceptual 32-bit Peripheral ID Register.

Figure 3.29. dmc_periph_id Register bit assignments

The following sections describe the dmc_periph_id Registers:

DMC Peripheral Identification Register 0

The dmc_periph_id_0 Register is hard-coded and the fields within the register indicate the value. Table 3.26 lists the register bit assignments.

Table 3.26. dmc_periph_id_0 Register bit assignments

BitsName

Description

[31:8]-

Read undefined

[7:0]

part_number_0

These bits read back as 0x40

DMC Peripheral Identification Register 1

The dmc_periph_id_1 Register is hard-coded and the fields within the register indicate the value. Table 3.27 lists the register bit assignments.

Table 3.27. dmc_periph_id_1 Register bit assignments

BitsName

Description

[31:8]-

Read undefined

[7:4]

designer_0

These bits read back as 0x1

[3:0]

part_number_1

These bits read back as 0x3

DMC Peripheral Identification Register 2

The dmc_periph_id_2 Register is hard-coded and the fields within the register indicate the value. Table 3.28 lists the register bit assignments.

Table 3.28. dmc_periph_id_2 Register bit assignments

BitsName

Description

[31:8]-

Read undefined

[7:4]

revision

These bits read back as 0x1
[3:0]

designer_1

These bits read back as 0x4

DMC Peripheral Identification Register 3

The dmc_periph_id_3 Register is hard-coded and the fields within the register indicate the value of 0x0. Table 3.29 lists the register bit assignments.

Table 3.29. dmc_periph_id_3 Register bit assignments

BitsName

Description

[31:8]-

Read undefined.

[7:4]-Reserved for future use, read undefined.
[3:0]Customer ModifiedCustomer modified number. 0 from ARM.
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