3.3.25. DMC PrimeCell Identification Registers <0-3> at 0xFF0-0xFFC

The dmc_pcell_id Registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a single register that holds a 32-bit component ID value. The register can be used for automatic BIOS configuration. The pcell_id Register is set to 0xB105F00D. The register can be accessed with one wait state. Table 3.30 lists the register bit assignments.

Table 3.30. dmc_pcell_id Register bit assignments

Component ID registerCompID0-3 register
BitsValueRegisterBits

Description

--dmc_pcell_id_3[31:8]

Read undefined

[31:24]0xB1

dmc_pcell_id_3

[7:0]

These bits read back as 0xB1

--dmc_pcell_id_2[31:8]

Read undefined

[23:16]0x05dmc_pcell_id_2[7:0]

These bits read back as 0x05

--dmc_pcell_id_1[31:8]

Read undefined

[15:8]0xF0dmc_pcell_id_1[7:0]

These bits read back as 0xF0

--dmc_pcell_id_0[31:8]

Read undefined

[7:0]0x0Ddmc_pcell_id_0[7:0]

These bits read back as 0x0D

Figure 3.30 shows the register bit assignments.

Figure 3.30. dmc_pcell_id Register bit assignments

The following sections describe the dmc_pcell_id Registers:

Note

These registers cannot be read in the Reset state.

DMC PrimeCell Identification Register 0

The dmc_pcell_id_0 Register is hard-coded and the fields within the register indicate the value. Table 3.31 lists the register bit assignments.

Table 3.31. dmc_pcell_id_0 Register bit assignments

BitsNameFunction
[31:8]-Reserved, read undefined
[7:0]dmc_pcell_id_0These bits read back as 0x0D

DMC PrimeCell Identification Register 1

The dmc_pcell_id_1 Register is hard-coded and the fields within the register indicate the value. Table 3.32 lists the register bit assignments.

Table 3.32. dmc_pcell_id_1 Register bit assignments

BitsNameFunction
[31:8]-Reserved, read undefined
[7:0]dmc_pcell_id_1These bits read back as 0xF0

DMC PrimeCell Identification Register 2

The dmc_pcell_id_2 Register is hard-coded and the fields within the register indicate the value. Table 3.33 lists the register bit assignments.

Table 3.33. dmc_pcell_id_2 Register bit assignments

BitsNameFunction
[31:8]-Reserved, read undefined
[7:0]dmc_pcell_id_2These bits read back as 0x5

DMC PrimeCell Identification Register 3

The dmc_pcell_id_3 Register is hard-coded and the fields within the register indicate the value. Table 3.34 lists the register bit assignments.

Table 3.34. dmc_pcell_id_3 Register bit assignments

BitsNameFunction
[31:8]-Reserved, read undefined
[7:0]dmc_pcell_id_3These bits read back as 0xB1
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