PrimeCell® AHB DDR and NAND Memory Controller (PL244) Technical Reference Manual A.4. DMC memory interface signals

A.4. DMC memory interface signals

Table A.3 lists the DMC memory interface signals.

Table A.3. DMC memory interface signals

Name	Type	Source/ destination	Description
dmc_fbclk_in	Input	Memory	Fed back clock
dmc_dqs_in_<0-1>	Input	Memory	Data strobe in
dmc_dqs_in_n_<0-1>	Input	Memory	Inverted data strobe in
dmc_dq_in[15:0]	Input	Memory	Data in
dmc_clk_out[3:0]	Output	Memory	Clock out
dmc_ras_n	Output	Memory	Row address strobe
dmc_cas_n	Output	Memory	Column address strobe
dmc_we_n	Output	Memory	Write enable
dmc_cke	Output	Memory	Clock enable
dmc_cs_n[3:0]	Output	Memory	Chip select
dmc_add[15:0]	Output	Memory	Address
dmc_ba[1:0]	Output	Memory	Bank address
dmc_ap	Output	Memory	Auto precharge
dmc_dqs_out_<0-1>	Output	Memory	Data strobe out
dmc_dq_out[15:0]	Output	Memory	Data out
dmc_data_en	Output	Memory	Data enable
dmc_dqm[1:0]	Output	Memory	Data mask
dmc_use_ebi	Input	Memory	Use EBI tie-off
dmc_ebibackoff	Input	Memory	EBI back off
dmc_ebigrant	Input	Memory	EBI grant
dmc_ebireq	Output	Memory	EBI request

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