A.5. DMC miscellaneous signals

Table A.4 lists the DMC miscellaneous signals.

Table A.4. DMC miscellaneous signals

NameType

Source/

destination

Description
dmc_qos_override[15:0]InputSystemQoS override
dmc_user_status[7:0]InputSystemUser signals to the configuration port
dmc_memory_width[1:0]InputSystemMemory width tie-off
dmc_asyncInputSystemAHB clock synchronous to memory clock
dmc_msyncInputSystemMemory clock synchronous to AHB clock
dmc_a_gt_m_syncInputSystemAHB clock synchronous to and greater than memory clock
dmc_cke_initInputSystemCKE polarity tie-off
dmc_dqm_initInputSystemDQM polarity tie-off
dmc_user_config[7:0]OutputSystemUser signals from the configuration port
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