A.7. SMC miscellaneous signals

Table A.6 lists the SMC miscellaneous signals.

Table A.6. SMC miscellaneous signals

NameType

Source/

destination

Description
smc_async0InputTie-offSMC clock synchronous to memory clock
smc_msync0InputTie-offMemory clock synchronous to SMC clock
smc_a_gt_m0_syncInputTie-offWhen HIGH, indicates that smc_aclk is greater than and synchronous to smc_mclk0
smc_address_mask0_0[7:0]InputTie-offAddress mask for chip select 0
smc_address_match0_0[7:0]InputTie-offAddress match for chip select 0
smc_address_mask0_1[7:0]InputTie-offAddress mask for chip select 1
smc_address_match0_1[7:0]InputTie-offAddress match for chip select 1
smc_remap_0InputTie-offRemap
smc_nand_mw_0InputTie-offMemory width tie-off
smc_nand_csl_0InputTie-offNAND memory requires CS LOW during read-busy times
smc_nand_booten_0InputTie-offEnable NAND booting functionality
smc_user_status[7:0]InputTie-offUser signals to the configuration port
smc_user_config[7:0]OutputSystemUser signals from the configuration port
smc_intOutputSystemInterrupt
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