PrimeCell ® AHBDDR and SRAM/NOR Memory Controller (PL245) Technical Reference Manual

Revision: r0p1

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the AHB MC
1.1.1. AHB interface
1.1.2. AHB to APB bridge
1.1.3. Bus matrix
1.1.4. DMC
1.1.5. SMC
1.1.6. Clock domains
1.1.7. Low-power interfaces
1.2. Supported devices
2. Functional Overview
2.1. Functional description
2.1.1. AHB interface
2.1.2. AHB to APB bridge
2.1.3. Bus matrix
2.1.4. Clock domains
2.1.5. Low-power interface
2.2. DMC
2.2.1. Arbiter
2.2.2. Memory manager
2.2.3. APB slave interface
2.2.4. Memory interface
2.2.5. Pad interface
2.3. SMC
2.3.1. SMC interface
2.3.2. APB slave interface
2.3.3. Format
2.3.4. Memory manager
2.3.5. Memory interface
2.3.6. Pad interface
2.3.7. Interrupts
2.4. Functional operation
2.4.1. AHB interface operation
2.4.2. AHB to APB bridge operation
2.4.3. Bus matrix operation
2.4.4. Clock domain operation
2.4.5. Low-power interface operation
2.5. DMC functional operation
2.5.1. Clocking and resets
2.5.2. Miscellaneous signals
2.5.3. DMC slave interface
2.5.4. Arbiter operation
2.5.5. Memory manager operation
2.5.6. APB slave interface operation
2.5.7. Memory interface operation
2.5.8. Pad interface operation
2.5.9. Initialization
2.5.10. Power-down support and usage model
2.6. SMC functional operation
2.6.1. Operating states
2.6.2. Clocking and resets
2.6.3. Miscellaneous signals
2.6.4. APB slave interface operation
2.6.5. Format block
2.6.6. Memory manager operation
2.6.7. Interrupts operation
2.6.8. Memory interface operation
3. Programmer’s Model
3.1. About the programmer’s model
3.2. DMC Register summary
3.3. DMC Register descriptions
3.3.1. DMC Memory Controller Status Registerat 0x0000
3.3.2. DMC Memory Controller Command Registerat 0x0004
3.3.3. DMC Direct Command Register at 0x0008
3.3.4. DMC Memory Configuration Registerat 0x000C
3.3.5. DMC Refresh Period Register at 0x0010
3.3.6. DMC CAS Latency Register at 0x0014
3.3.7. DMC t_dqss Register at 0x0018
3.3.8. DMC t_mrd Register at 0x001C
3.3.9. DMC t_ras Register at 0x0020
3.3.10. DMC t_rc Register at 0x0024
3.3.11. DMC t_rcd Register at 0x0028
3.3.12. DMC t_rfc Register at 0x002C
3.3.13. DMC t_rp Register at 0x0030
3.3.14. DMC t_rrd Register at 0x0034
3.3.15. DMC t_wr Register at 0x0038
3.3.16. DMC t_wtr Register at 0x003C
3.3.17. DMC t_xp Register at 0x0040
3.3.18. DMC t_xsr Register at 0x0044
3.3.19. DMC t_esr Register at 0x0048
3.3.20. DMC id_<0-5>_cfg Registers at 0x0100
3.3.21. DMC chip_<0-3>_cfg Registers at0x0200
3.3.22. DMC user_status Register at 0x0300
3.3.23. DMC user_config Register at 0x0304
3.3.24. DMC Peripheral Identification Registers <0-3> at0x0FE0-0x0FEC
3.3.25. DMC PrimeCell Identification Registers <0-3> at0xFF0-0xFFC
3.4. SMC Register summary
3.5. SMC Register descriptions
3.5.1. SMC Memory Controller Status Registerat 0x1000
3.5.2. SMC Memory Interface ConfigurationRegister at 0x1004
3.5.3. SMC Set Configuration Register at0x1008
3.5.4. SMC Clear Configuration Register at0x100C
3.5.5. SMC Direct Command Register at 0x1010
3.5.6. SMC Set Cycles Register at 0x1014
3.5.7. SMC Set Opmode Register at 0x1018
3.5.8. SMC Refresh Period 0 Register at 0x1020
3.5.9. SMC SRAM Cycles Registers <0-3> at0x1100, 0x1120, 0x1140, 0x1160
3.5.10. SMC Opmode Registers <0-3> at 0x1104,0x1124, 0x1144, 0x1164
3.5.11. SMC User Status Register at 0x1200
3.5.12. SMC User Configuration Register at0x1204
3.5.13. SMC Peripheral Identification Registers <0-3> at0x1FE0-0x1FEC
3.5.14. SMC PrimeCell Identification Registers <0-3> at0x1FF0-0x1FFC
4. Programmer’s Model for Test
4.1. DMC and SMC integration test registers
4.1.1. DMC Integration Configuration Registerat 0x0E00
4.1.2. DMC Integration Inputs Register at0x0E04
4.1.3. DMC Integration OutputsRegister at 0x0E08
4.1.4. SMC Integration Configuration Registerat 0x1E00
4.1.5. SMC Integration Inputs Register at0x1E04
4.1.6. SMC Integration Outputs Register at0x1E08
5. Device Driver Requirements
5.1. DMC memory initialization
5.2. SMC memory initialization
A. Signal Descriptions
A.1. About the signals list
A.2. Clocks and resets
A.3. AHB signals
A.4. DMC memory interface signals
A.5. DMC miscellaneous signals
A.6. SMC memory interface signals
A.7. SMC miscellaneous signals
A.8. Low-power interface
A.9. Configuration signals
A.10. Scan chain signals

List of Figures

1. Key to timing diagram conventions
1.1. AHB MC (PL245) configuration
2.1. AHB MC (PL245) configuration
2.2. AHB MC (PL245) clock domains
2.3. DMC block diagram
2.4. dmc_aclk domain FSM diagram
2.5. Low-power interface channel signals
2.6. dmc_mclk domain FSM diagram
2.7. DMC Pad interface external connections
2.8. SMC block diagram
2.9. SMC SRAM pad interface external connections
2.10. Big-endian implementation
2.11. AHBC memory map
2.12. Memory map
2.13. Request to enter low-power mode
2.14. AHB domain denying a low-power request
2.15. Accepting requests
2.16. Command control output timing
2.17. Activate to read or write commandtiming, tRCD
2.18. Bank activate to bank activate orauto-refresh command timing, tRC
2.19. Bank activate to different bank activatefor a memory timing, tRRD
2.20. Precharge to command and auto-refreshtiming, tRP and tRFC
2.21. Activate to precharge, and prechargeto precharge timing, tRAS and tRP
2.22. Mode register write to command timing,tMRD
2.23. Self-refresh entry and exit timing,tESR and tXSR
2.24. Power down entry and exit timing,tXP
2.25. Data output timing, tWTR
2.26. Data output timing, tDQSS =1
2.27. Data input timing
2.28. DMC system state transitions
2.29. smc_aclk domain FSM diagram
2.30. Chip configuration registers
2.31. Device pin mechanism
2.32. Software mechanism
2.33. Asynchronous read
2.34. Asynchronous read in multiplexed-mode
2.35. Asynchronous write
2.36. Asynchronous write in multiplexed-mode
2.37. Page read
2.38. Synchronous burst read
2.39. Synchronous burst read in multiplexed-mode
2.40. Synchronous burst write
2.41. Synchronous burst write in multiplexed-mode
2.42. Synchronous read and asynchronouswrite
3.1. DMC and SMC register map
3.2. DMC configuration register map
3.3. DMC id configuration register map
3.4. DMC chip configuration register map
3.5. DMC peripheral and PrimeCell Identificationconfiguration register map
3.6. dmc_memc_status Register bit assignments
3.7. dmc_memc_cmd Register bit assignments
3.8. dmc_direct_cmd Register bit assignments
3.9. dmc_memory_cfg Register bit assignments
3.10. dmc_refresh_prd Register bit assignments
3.11. dmc_cas_latency Register bit assignments
3.12. dmc_t_dqss Register bit assignments
3.13. dmc_t_mrd Register bit assignments
3.14. dmc_t_ras Register bit assignments
3.15. dmc_t_rc Register bit assignments
3.16. dmc_t_rcd Register bit assignments
3.17. dmc_t_rfc Register bit assignments
3.18. dmc_t_rp Register bit assignments
3.19. dmc_t_rrd Register bit assignments
3.20. dmc_t_wr Register bit assignments
3.21. dmc_t_wtr Register bit assignments
3.22. dmc_t_xp Register bit assignments
3.23. dmc_t_xsr Register bit assignments
3.24. dmc_t_esr Register bit assignments
3.25. dmc_id_<0-5>_cfg Registers bitassignments
3.26. dmc_chip_<0-3>_cfg Registers bitassignments
3.27. dmc_user_status Register bit assignments
3.28. dmc_user_config Register bit assignments
3.29. dmc_periph_id Register bit assignments
3.30. dmc_pcell_id Register bit assignments
3.31. SMC configuration register map
3.32. SMC chip configuration register map
3.33. SMC user configuration register map
3.34. SMC peripheral and PrimeCell identificationconfiguration register map
3.35. smc_memc_status Register bit assignments
3.36. smc_memif_cfg Register bit assignments
3.37. smc_memc_cfg_set Register bit assignments
3.38. smc_memc_cfg_clr Register bit assignments
3.39. smc_direct_cmd Register bit assignments
3.40. smc_set_cycles Register bit assignments
3.41. smc_set_opmode Register bit assignments
3.42. smc_refresh_period_0 Register bitassignments
3.43. smc_sram_cycles Register bit assignments
3.44. smc_opmode Register bit assignments
3.45. smc_user_status Register bit assignments
3.46. smc_user_config Register bit assignments
3.47. smc_periph_id Register bit assignments
3.48. smc_pcell_id Register bit assignments
4.1. DMC integration test register map
4.2. SMC integration test register map
4.3. dmc_int_cfg Register bit assignments
4.4. dmc_int_inputs Register bit assignments
4.5. dmc_int_outputs Register bit assignments
4.6. smc_int_cfg Register bit assignments
4.7. smc_int_inputs Register bit assignments
4.8. smc_int_outputs Register bit assignments
5.1. DMC and memory initialization sheet1 of 2
5.2. DMC and memory initialization sheet2 of 2
5.3. SMC and memory initialization sheet1 of 3
5.4. SMC and memory initialization sheet 2 of 3
5.5. SMC and memory initialization sheet3 of 3
A.1. AHB MC (PL245) grouping of signals

List of Tables

2.1. Dynamic memory clocking options
2.2. Static memory clocking options
2.3. Example DDR setup
2.4. Valid system states for FSMs
2.5. Recommended power states
2.6. Asynchronous read opmode chip register settings
2.7. Asynchronous read SRAM cycles register settings
2.8. Asynchronous read in multiplexed-mode opmode chip registersettings
2.9. Asynchronous read in multiplexed-mode SRAM cycles registersettings
2.10. Asynchronous write opmode chip register settings
2.11. Asynchronous write SRAM cycles register settings
2.12. Asynchronous write in multiplexed-mode opmode chip register settings
2.13. Asynchronous write in multiplexed-mode SRAM cycles register settings
2.14. Page read opmode chip register settings
2.15. Page read SRAM cycles register settings
2.16. Synchronous burst read opmode chip register settings
2.17. Synchronous burst read SRAM cycles register settings
2.18. Synchronous burst read in multiplexed-mode opmode chip register settings
2.19. Synchronous burst read in multiplexed-mode read SRAM cycles registersettings
2.20. Synchronous burst write opmode chip register settings
2.21. Synchronous burst write SRAM cycles register settings
2.22. Synchronous burst write in multiplexed-mode opmode chip register settings
2.23. Synchronous burst write in multiplexed-mode SRAM cycles register settings
2.24. Synchronous read and asynchronous write opmode chip register settings
2.25. Synchronous read and asynchronous write opmode chip register settings
3.1. DMC register summary
3.2. dmc_memc_status Register bit assignments
3.3. dmc_memc_cmd Register bit assignments
3.4. dmc_direct_cmd Register bit assignments
3.5. dmc_memory_cfg Register bit assignments
3.6. dmc_refresh_prd Register bit assignments
3.7. dmc_cas_latency Register bit assignments
3.8. dmc_t_dqss Register bit assignments
3.9. dmc_t_mrd Register bit assignments
3.10. dmc_t_ras Register bit assignments
3.11. dmc_t_rc Register bit assignments
3.12. dmc_t_rcd Register bit assignments
3.13. dmc_t_rfc Register bit assignments
3.14. dmc_t_rp Register bit assignments
3.15. dmc_t_rrd Register bit assignments
3.16. dmc_t_wr Register bit assignments
3.17. dmc_t_wtr Register bit assignments
3.18. dmc_t_xp Register bit assignments
3.19. dmc_t_xsr Register bit assignments
3.20. dmc_t_esr Register bit assignments
3.21. dmc_id_<0-5>_cfg Registers bit assignments
3.22. dmc_chip_<0-3>_cfg Registers bit assignments
3.23. dmc_user_status Register bit assignments
3.24. dmc_user_status Registers bit assignments
3.25. dmc_periph_id Register bit assignments
3.26. dmc_periph_id_0 Register bit assignments
3.27. dmc_periph_id_1 Register bit assignments
3.28. dmc_periph_id_2 Register bit assignments
3.29. dmc_periph_id_3 Register bit assignments
3.30. dmc_pcell_id Register bit assignments
3.31. dmc_pcell_id_0 Register bit assignments
3.32. dmc_pcell_id_1 Register bit assignments
3.33. dmc_pcell_id_2 Register bit assignments
3.34. dmc_pcell_id_3 Register bit assignments
3.35. Register summary
3.36. smc_memc_status Register bit assignments
3.37. smc_memif_cfg Register bit assignments
3.38. smc_memc_cfg_set Register bit assignments
3.39. smc_memc_cfg_clr Register bit assignments
3.40. smc_directcmd Register bit assignments
3.41. smc_set_cycles Register bit assignments
3.42. smc_set_opmode Register bit assignments
3.43. smc_refresh_period_0 Register bit assignments
3.44. smc_sram_cycles Register bit assignments
3.45. smc_opmode Register bit assignments
3.46. smc_user_status Register bit assignments
3.47. smc_user_config Register bit assignments
3.48. smc_periph_id Register bit assignments
3.49. smc_periph_id_0 Register bit assignments
3.50. smc_periph_id_1 Register bit assignments
3.51. smc_periph_id_2 Register bit assignments
3.52. smc_periph_id_3 Register bit assignments
3.53. smc_pcell_id Register bit assignments
3.54. smc_pcell_id_0 Register bit assignments
3.55. smc_pcell_id_1 Register bit assignments
3.56. smc_pcell_id_2 Register bit assignments
3.57. smc_pcell_id_3 Register bit assignments
4.1. DMC integration test register summary
4.2. SMC integration test register summary
4.3. dmc_int_cfg Register bit assignments
4.4. dmc_int_inputs Register bit assignments
4.5. dmc_int_outputs Register bit assignments
4.6. smc_int_cfg Register bit assignments
4.7. smc_int_inputs Register bit assignments
4.8. smc_int_outputs Register bit assignments
A.1. Clocks and resets
A.2. AHB signals
A.3. DMC memory interface signals
A.4. DMC miscellaneous signals
A.5. SMC memory interface signals
A.6. SMC miscellaneous signals
A.7. Low-power interface signals
A.8. Configuration signals
A.9. Scan chain signals

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 11May 2006 First release for r0p0
Revision B 20December 2006 Updated for r0p1
Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0393B