2.2.2. Master interfaces

The AMBA Network Interconnect supports the following master interfaces:

AXI master interfaces

The network supports the full AXI protocol using an AXI master interface.

Configuration options

You can configure the following AXI options:

  • Address width of 32-64 bits.

  • Data width of 32, 64, 128, or 256 bits.

  • Data width upsize function that Upsizing data width function describes.

  • User sideband signal width of 0-32 bits.

  • Data width downsize function that Downsizing data width function describes.

  • Frequency domain crossing of type:

    • ASYNC

    • SYNC 1:1

    • SYNC 1:n

    • SYNC n:1

    • SYNC n:m.

  • Support for the full AXI protocol.

    Note

    You can reduce the gate count and increase the performance if all attached master that can access the master interface does not create any AXI lock transactions.

  • Write issuing capability of 1-32 transactions.

  • Read issuing capability of 1-32 transactions.

  • Buffering that FIFO and clocking function describes.

  • Timing isolation:

    • from the external slave

    • from the network.

AHB master interfaces

The network can support the full AHB-Lite master protocol and you can configure the network to provide an AHB-Lite mirrored slave protocol. Table 2.2 shows the mapping of AXI burst types to AHB burst types.

Table 2.2. AXI burst type to AHB burst type mapping

AxBURSTAxLENHBURSTNotes
FIXED-SINGLEThis is a series of singles and the number depends on the AxLEN setting
INCR1SINGLE-
-4INCR4-
-8INCR8-
-16INCR16-
-2, 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15INCRUndefined length
WRAP2SINGLETwo transfers
-4WRAP4-
-8WRAP8-
-16WRAP16-

Note

Transactions from AHB slave interfaces are output as INCR transactions of an undefined length.

If the AHB protocol conversion function receives an unaligned address, or a write data beat without all the byte strobes set, the AMBA Network Interconnect detects it, and a programmable enable bit permits the network to create a DECERR response.

Note

  • If you set the force_incr programmable bit, see Table 3.3, and a beat is received that has no write data strobes set, that write data beat is replaced with an IDLE beat.

  • You can configure the inclusion of the programmable enable bit to create a reduced gate count implementation.

See Chapter 3 Programmers Model. The network still transmits the unaligned address transfer into the AHB domain, but it aligns the address by forcing the lower address bits of the transaction’s size to zeros.

The network breaks any transactions that cross a 1KB boundary into two AHB INCR bursts. You can configure a programmable option, named force_incr, see Table 3.3, that maps all transactions that are to be output to the AHB domain to be an undefined length INCR.

If the AXI burst is part of a locked sequence, the AHB-Lite translation keeps HMASTLOCK asserted across the boundary to ensure that the burst atomicity is not compromised. For write transactions, AHB responses are merged into a single AXI buffered response. The merged response is an AXI SLAVE ERROR if any of the AHB-Lite data beats have an AHB ERROR.

Configuration options

You can configure the following options for the AHB interface:

  • Address width of 32-64 bits.

  • Data width of 32, 64, 128, or 256 bits.

  • Data width upsize function that Upsizing data width function describes.

  • Data width downsize function that Downsizing data width function describes.

  • Frequency domain crossing of the following types:

    • ASYNC

    • SYNC 1:1

    • SYNC 1:n

    • SYNC n:1

    • SYNC n:m.

  • Security of the following types:

    Secure

    Only secure transactions can access components attached to this master interface.

    Non-secure

    Both secure and non-secure transactions can access components attached to this master interface.

    Boot time secure

    You can use software to configure whether it permits secure and non-secure transactions to access components attached to this master using the Secure and Non-secure options above.

  • Support for the full AHB-Lite master protocol.

  • Timing isolation:

    • from the external slave

    • from the network.

APB master interfaces

You can configure the APB interface to support a mixture of APB2 or APB3. The APB data width is always 32-bit, and it is therefore never necessary for the APB interface to require the upsize function. The APB interface can ignore AXI writes strobes. If the network receives a write transaction with all of the write strobes negated, then it does not perform the write.

Note

APB SLVERR responses are converted to AXI SLVERR responses.

Any transaction that the network receives without all four WSTRBs asserted or negated still goes ahead. This means that erroneous data bytes might be written to the slave. The masters accessing the APB interface ensure that only WORD writes access the APB sub-system. The address and data widths are fixed as follows:

  • address width of 32-bit

  • data width of 32-bit.

Note

Although the AMBA Network Interconnect only outputs 32 address bits, you can configure the APB address of any peripheral to be anywhere in the address map.

Configuration options

You can configure the following options:

  • data width downsize function that Downsizing data width function describes

  • frequency domain crossing for the majority of APB ports of the following types:

    • ASYNC

    • SYNC 1:1

    • SYNC 1:n

    • SYNC n:1

    • SYNC n:m.

  • buffering that FIFO and clocking function describes

  • 1-16 supported APB slaves

  • configurable address region sizes

  • non-contiguous address regions

  • you can configure each APB slave for:

    • APB2 or APB3

    • asynchronous interface to the majority of APB ports.

  • security of the following types:

    • secure for each APB port

    • non-secure for each APB port

    • boot secure for all APB ports.

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