1.4. Product revisions

This section describes differences in functionality between product revisions of the AMBA Network Interconnect (NIC-301):


Contains the following differences in functionality:

  • support for 128-bit data width on AXI and all AHB variant interfaces

  • support for n-bit addressing on AXI and all AHB variant interfaces, where n is 32-64 bit inclusive

  • the decode register is a slave interface property instead of a global property

  • single-slave-per-ID Cyclic Dependency Avoidance Scheme (CDAS)

  • ID register and configuration data

  • use of updated synchronous bridges

  • use of an AHB to AXI bridge optimized for accessing memory where appropriate.


Contains the following differences in functionality:

  • Separation of arbitration of AW and AR channels so that a slave can accept transactions from two different masters simultaneously.

  • Changes to the way that the AMBA Network Interconnect handles LOCKed transactions.

  • Configurable arbitration schemes, that can be:

    • programmable Least Recently Granted (LRG), the scheme present in r1p0

    • a non-programmable Round-Robin (RR) scheme.

  • You can select and configure arbitration schemes for each master interface.

  • The APB programming interface enables you to program and interrogate the new, separate arbitration schemes.

  • The AHB to AXI bridge is optimized for accessing memory is updated with performance enhancements, and to fix a defect.

  • The way arbitration schemes are described has changed to enable you to select and configure arbitration schemes.

  • The Quality of Service (QoS) tidemark value now represents the maximum permitted number of active transactions before the QoS mechanism is activated, instead of the minimum number of unused slots before the mechanism is activated. This means the combined acceptance capability attribute of a master interface is no longer required.


Contains the following differences in functionality:

  • Updates to the example synthesis scripts.

  • Addition of a programmable version of the fixed round-robin arbitration scheme.

  • Shortening some long paths to improve synthesis performance.

  • A change to the way register slices are instantiated. This makes it easier to use them to resolve timing issues during synthesis.

  • The choice of CDAS is independent for reads and writes.

  • Additional configuration option for the single-slave-per-ID CDAS that permits only a single data-active write transaction to be in progress.


Contains the following differences in functionality:

  • Network of interconnects instead of a single interconnect

  • Optimized translation latency replaces additive translation latency

  • Single cycle arbitration instead of arbitration switching delay

  • Enhanced buffering to reduce stalls

  • Multiple outstanding downsizer transactions instead of limited outstanding downsizer transactions

  • Upsizer packs data into the wide bus, instead of an expander, for data width changes

  • Global dynamic QoS instead of local static QoS

  • Internally programmable instead of externally programmed

  • System-level address map replaces an address map for each interconnect

  • Extended timing closure options replace limited timing closure options

  • 256-bit maximum data width instead of 128-bit maximum data width

  • Multi-region slave support replaces a single region per slave

  • Write FIFO, transaction release control instead of fixed write transaction release point.

See Appendix A Revisions.

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