3.2.1. Register block types

The following types of register block exist:

Figure 3.1 shows the address map of the programmers model. It contains one fixed base address, and all the other programmers model 4KB blocks are stacked. All address regions are packed.

Figure 3.1. Address map of the programmers model


The type defines the number of register blocks in a single AMBA Network Interconnect configuration. Table 3.1, Table 3.2, and Table 3.3 show the register block sub-types for each of the main types.

Table 3.4 shows the address region control registers and Table 3.5 shows the peripheral ID registers.

Note

In Table 3.1 to Table 3.5, reserved means:

  • read as zeros

  • writes are ignored.

AHB only means that this register is interpreted as reserved if the interface is not AHB.

Table 3.1 shows the registers when one register block exists for each ASIB.

Table 3.1. One register block for each ASIB

Address

offset

TypeWidth

Reset

value

NameDescription
0x000----Reserved.
0x004----Reserved.
0x008----Reserved.
0x00C----Reserved.
0x020RW34sync_mode

Only if you configure the block as a programmable FIFO as follows:

0

sync 1:1.

1

sync n:1.

2

sync 1:n.

3

sync m:n.

4

async.

5

reserved.

6

reserved.

7

reserved.

0x024RW10fn_mod2Bypass merge, only if upsizing or downsizing, see Upsizing data width function, Downsizing data width function, and Bypass merge.
0x028RW30fn_mod_ahb

This register is valid for AHB interfaces only. You can configure this register as follows:

0

rd_incr_override.

1

wr_incr_override.

2

lock_override.

See Lock transactions for information on overriding locks. See Combination 4 for information on wr_incr_override and rd_incr_override.

0x02C - 0x03C----Reserved.
0x040RW40wr_tidemarkValid only with a FIFO for the WFIFO channel, and if not an AHB slave interface. See FIFO and clocking function for information on wr_tidemark.
0x044 - 0x0FC----Reserved.
0x100RW40read_qosRead channel QoS value.
0x104RW40write_qosWrite channel quality value.
0x108RW20fn_mod_iss

Issuing functionality modification register.

Issuing override, sets block issuing capability to one outstanding transaction, and you can configure the bits as follows:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x10C - 0xFFC----Reserved.

Table 3.2 shows the registers when one register block exists for each IB.

Table 3.2. One register block for each IB

Address

offset

TypeWidth

Reset

value

NameDescription
0x000----Reserved.
0x004----Reserved.
0x008----Reserved.
0x00C----Reserved.
0x020RW34Sync_mode

Only with a FIFO for all channels, and you can configure the bits as a clock domain boundary as follows:

0

sync 1:1.

1

sync n:1.

2

sync 1:n.

3

sync m:n.

4

async.

5

reserved.

6

reserved.

7

reserved.

0x024RW10fn_mod2Bypass merge, only if upsizing or downsizing. See Upsizing data width function, Downsizing data width function, and Bypass merge.
0x028 - 0x03C----Reserved.
0x040RW40wr_tidemarkValue, only with a FIFO for the WFIFO channel.
0x044----Reserved.
0x100----Reserved.
0x104----Reserved.
0x108RW20fn_mod_iss

Issuing functionality modification register.

Issuing override, sets block issuing capability to one transaction and you can configure the bits as follows:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.

0x10CRW10--
0x110RW10--

Table 3.3 shows the registers when one register block exists for each AMIB.

Table 3.3. One register block for each AMIB

Address

offset

TypeWidth

Reset

value

NameDescription
0x000----Reserved.
0x004----Reserved.
0x008----Reserved.
0x00C----Reserved.
0x020RW34Sync_mode

Only with a FIFO for all channels, and you can configure the bits to create different clock domain boundaries as follows:

0

sync 1:1.

1

sync n:1.

2

sync 1:n.

3

sync m:n.

4

async.

5

reserved.

6

reserved.

7

reserved.

0x024RW10fn_mod2Bypass merge, only if upsizing or downsizing, see Upsizing data width function and Downsizing data width function.
0x028----Reserved.
0x040----Reserved.
0x044-2-ahb_cntl

AHB only, and you can configure the bits as follows:

0

decerr_en.

1

force_incr.

See AHB master interfaces.

0x100----Reserved.
0x104----Reserved.
0x108RW20fn_mod_iss

Issuing functionality modification register.

Issuing override, sets block issuing capability to be forced to one transaction and you can configure the bits as follows:

0

Read issuing, read_iss_override.

1

Write issuing, write_iss_override.


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