CoreSight™ PTM™-A9 Technical Reference Manual 2.3.12. Configuration Code Extension Register, ETMCCER

The Configuration Code Extension Register, ETMCCER, provides additional information about the configuration of the PTM-A9. It is:

Figure 2.8 shows the bit assignments for the Configuration Code Extension Register.

Figure 2.8. Configuration Code Extension Register format

Table 2.11 shows the bit assignments for the Configuration Code Extension Register.

Table 2.11. Configuration Code Extension Register bit functions

Bits	Function
[31:26]	Reserved, RAZ on reads.
[25]	b0 - Timestamps not generated for DMB/DSB.
[24]	b0 - DMB/DSB instructions are not treated as waypoints.
[23]	b1 - Return stack implemented.
[22]	b1 - Timestamping implemented.
[21:16]	Reserved, RAZ on reads.
[15:13]	b000 - Specifies the number of instrumentation resources.
[12]	Reserved, RAO.
[11]	b1 - Indicates that all registers, except some Integration Test Registers, are readable. See Using the Integration Test Registers for details of the access permission to the Integration Test Registers. Registers with names that start with IT are the Integration Test Registers, for example ITATBCTR1.
[10:3]	b00011101 - Specifies the size of the extended external input bus, 29.
[2:0]	b010 - Specifies the number of extended external input selectors, 2.

Copyright © 2008 ARM Limited. All rights reserved.	ARM DDI 0401A
Non-Confidential
PDF version