CoreSight™ PTM™-A9 Technical Reference Manual 2.3.18. Integration registers

2.3.18. Integration registers

A CoreSight PTM can provide registers that let you test your integration of the PTM into your design. This section describes the integration registers that are implemented for the PTM-A9. It contains the following sections:

Using the Integration Test Registers

Table 2.14 lists the Integration Test Registers implemented by the PTM-A9.

Table 2.14. Integration Test Registers

Base offset	Function	Type	Description
`0xEDC`	Miscellaneous Outputs	WO	See Miscellaneous Outputs Register, ITMISCOUT
`0xEE0`	Miscellaneous Inputs	RO	See Miscellaneous Inputs Register, ITMISCIN
`0xEE8`	Trigger	WO	See Trigger Register, ITTRIGGER
`0xEEC`	ATB Data	WO	See ATB Data 0 Register, ITATBDATA0
`0xEF0`	ATB Control 2	RO	See ATB Control 2 Register, ITATBCTR2
`0xEF4`	ATB Identification	WO	See ATB Identification Register, ITATBID
`0xEF8`	ATB Control 0	WO	See ATB Control 0 Register, ITATBCTR0

To access these registers you must first set bit [0] of the Integration Mode Control Register to 1. See Integration Mode Control Register, ETMITCTRL. When this bit is set:

You can use the write-only Integration Test Registers to set the outputs of some of the PTM-A9 signals. Table 2.15 lists the signals that you can control in this way.
You can use the read-only Integration Test Registers to read the state of some of the PTM-A9 input signals. Table 2.16 lists the signals that you can read in this way.

See the Program Flow Trace Architecture Specification for more information.

Table 2.15. Output signals that can be controlled by the Integration Test Registers

Register	Signal	Bit	Description
ITMISCOUT	PTMEXTOUT[1:0]	[9:8]	See Miscellaneous Outputs Register, ITMISCOUT
	PTMIDLEnACK	[5]
	PTMDBGREQ	[4]
ITATBDATA0	ATDATAM[31]	[4]	See ATB Data 0 Register, ITATBDATA0
	ATDATAM[23]	[3]
	ATDATAM[15]	[2]
	ATDATAM[7]	[1]
	ATDATAM[0]	[0]
ITTRIGGER	PTMTRIGGER	[0]	See Trigger Register, ITTRIGGER
ITATBID	ATIDM[6:0]	[6:0]	See ATB Identification Register, ITATBID
ITATBCTR0	ATBYTESM[9:8]	[9:8]	See ATB Control 0 Register, ITATBCTR0
	AFREADYM	[1]
	ATVALIDM	[0]

Table 2.16. Input signals that can be read by the Integration Test Registers

Register	Signal	Bit	Description
ITMISCIN	STANDBYWFI	[6]	See Miscellaneous Inputs Register, ITMISCIN
	PTMDBGACK	[4]
	PTMEXTIN[3:0]	[3:0]
ITATBCTR2	AFVALIDM	[1]	ATB Control 2 Register, ITATBCTR2
ITATBCTR2	ATREADYM	[0]	ATB Control 2 Register, ITATBCTR2

The CoreSight Components Technical Reference Manual gives a full description of the use of the Integration Test Registers to check integration. In brief:

When bit [0] of the Integration Mode Control Register is set, values written to the write-only Integration Test Registers map onto the specified outputs of the PTM-A9. For example, writing 0x3 to ITMISCOUT[9:8] causes EXTOUT[1:0] to take the value 0x3.
When bit [0] of the Integration Mode Control Register is set, values read from the read-only integration test registers correspond to the values of the specified inputs of the PTM-A9. For example, if you read ITMISCIN[3:0] you obtain the value of PTMEXTIN.

Miscellaneous Outputs Register, ITMISCOUT

The Miscellaneous Outputs Register, ITMISCOUT, controls signal outputs when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3B7, at offset 0xEDC
a write-only register.

Figure 2.11 shows the bit arrangement of the ITMISCOUT Register.

Figure 2.11. ITMISCOUT Register format

Table 2.17 shows how the bit values correspond with the ITMISCOUT Register functions.

Table 2.17. ITMISCOUT Register bit functions

Bits	Function
[31:10]	Reserved, Should Be Zero (SBZ) on writes
[9:8]	Drives the PTMEXTOUT[1:0] outputs
[7:6}	Reserved, Should Be Zero (SBZ) on writes
[5]	Drives the PTMIDLEnACK output
[4]	Drives the PTMDBGREQ output
[3:0]	Reserved, Should Be Zero (SBZ) on writes

Miscellaneous Inputs Register, ITMISCIN

The Miscellaneous Inputs Register, ITMISCIN, enables the values of signal inputs to be read when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3B8, at offset 0xEE0
a read-only register.

Figure 2.12 shows the bit arrangement of the ITMISCIN Register.

Figure 2.12. ITMISCIN Register format

Table 2.18 shows how the bit values correspond with the ITMISCIN Register functions. The value of these fields depend on the signals on the input pins when the register is read.

Table 2.18. ITMISCIN Register bit functions

Bits	Function
[31:7]	Reserved, RAZ on reads
[6]	Returns the value of the STANDBYWFI input
[5]	Reserved, RAZ on reads
[4]	Returns the value of the PTMDBGACK input
[3:0]	Returns the value of the EXTIN[3:0] inputs

Trigger Register, ITTRIGGER

The Trigger Register, ITTRIGGER, controls signal outputs when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3BA, at offset 0xEE8
a write-only register.

Figure 2.13 shows the bit arrangement of the ITTRIGGER Register.

Figure 2.13. ITTRIGGER Register format

Table 2.19 shows how the bit values correspond with the ITTRIGGER Register functions.

Table 2.19. ITTRIGGER Register bit functions

Bits	Function
[31:1]	Reserved, SBZ on writes
[0]	Drives the PTMTRIGGER output

ATB Data 0 Register, ITATBDATA0

The ATB Data 0 Register, ITATBDATA0, controls signal outputs when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3BB, at offset 0xEEC
a write-only register.

Figure 2.14 shows the bit arrangement of the ATB Data 0 Register.

Figure 2.14. ITATBDATA0 Register format

Table 2.20 shows how the bit values correspond with the ITATBDATA0 Register functions.

Table 2.20. ITATBDATA0 Register bit functions

Bits	Function
[31:5]	Reserved, SBZ on writes
[4]	Drives the ATDATAM[31] output
[3]	Drives the ATDATAM[23] output
[2]	Drives the ATDATAM[15] output
[1]	Drives the ATDATAM[7] output
[0]	Drives the ATDATAM[0] output

ATB Control 2 Register, ITATBCTR2

The ITATBCTR2 Register, ATB Control 2, enables the values of signal inputs to be read when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3BC, at offset 0xEF0
a read-only register.

Figure 2.15 shows the bit assignment of the ITATBCTR2 Register.

Figure 2.15. ITATBCTR2 Register format

Table 2.21 shows how the bit values correspond with the ITATBCTR2 Register functions. The value of these fields depend on the signals on the input pins when the register is read.

Table 2.21. ITATBCTR2 Register bit functions

Bits	Function
[31:2]	Reserved, RAZ on reads
[1]	Returns the value of the AFVALIDM input
[0]	Returns the value of the ATREADYM input

ATB Identification Register, ITATBID

The ATB Identification Register, ITATBID, controls signal outputs when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3BD, at offset 0xEF4
a write-only register.

Figure 2.16 shows the bit assignment of the ITATBID Register.

Figure 2.16. ITATBID Register format

Table 2.22 shows how the bit values correspond with the ITATBID Register functions.

Table 2.22. ITATBID Register bit functions

Bits	Function
[31:7]	Reserved, SBZ on writes
[6:0]	Drives the ATIDM[6:0] outputs

ATB Control 0 Register, ITATBCTR0

The ATB Control 0 Register, ITATBCTR0, controls signal outputs when bit [0] of the Integration Mode Control Register is set. It is:

register 0x3BE, at offset 0xEF8
a write-only register.

Figure 2.17 shows the bit assignment of the ITATBCTR0 Register.

Figure 2.17. ITATBCTR0 Register format

Table 2.23 shows how the bit values correspond with the ITATBCTR0 Register functions.

Table 2.23. ITATBCTR0 Register bit functions

Bits	Function
[31:10]	Reserved, SBZ on writes
[9:8]	Drives the ATBYTESM outputs
[7:2]	Reserved, SBZ on writes
[1]	Drives the AFREADYM output
[0]	Drives the ATVALIDM output

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