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 PDF version | |
| Home > Programmer’s Model > PTM-A9 register summary > TraceEnable Start/Stop Control Register, ETMTSSCR |
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The TraceEnable Start/Stop Control RegisteR, ETMTSSCR, specifies the single address comparators that hold the trace start and stop addresses that control the TraceEnable Start/Stop block. It is:
register 0x006,
at offset 0x018
a read/write register.
Figure 2.5 shows bit assignments for the TraceEnable Start/Stop Control Register.
Table 2.6 shows the bit assignments for the TraceEnable Start/Stop Control Register.
Table 2.6. TraceEnable Start/Stop Control Register bit assignments
Bit | Description |
|---|---|
| [31:24] | Reserved |
[23:16] | When a bit is set to 1, it selects a single address comparator (8-1) as a stop address for the TraceEnable Start/Stop block. For example, if you set bit [16] to 1 it selects single address comparator 1 as a stop address. |
| [15:8] | Reserved |
[7:0] | When a bit is set to 1, it selects a single address comparator (8-1) as a start address for the TraceEnable Start/Stop block. For example, if you set bit [0] to 1 it selects single address comparator 1 as a start address. |
| Copyright © 2008 ARM Limited. All rights reserved. | ARM DDI 0401A |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > PTM-A9 register summary > TraceEnable Start/Stop Control Register, ETMTSSCR |