CoreSight™ PTM™-A9 Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the Program Flow Trace Macrocell for the Cortex-A9 processor
1.1.1. PTM-A9 components
1.1.2. The CoreSight debug environment
1.2. Program Trace Macrocell configuration
1.3. Program Flow Trace macrocell components
1.3.1. Processor input FIFO
1.3.2. Trace blocks
1.3.3. Main FIFO
1.3.4. Clock domains
1.3.5. Level shifters
1.3.6. Cross-Trigger Interface
1.4. Prohibited regions for trace
1.5. Reset behavior
1.6. Product revisions
2. Programmer’s Model
2.1. Programming the PTM-A9
2.1.1. Using the Programming bit
2.1.2. Programming registers
2.2. Register short names
2.3. PTM-A9 register summary
2.3.1. Main Control Register, ETMCR
2.3.2. Configuration Code Register, ETMCCR
2.3.3. Status Register, ETMSR
2.3.4. System Configuration Register, ETMSCR
2.3.5. TraceEnable Control registers
2.3.6. TraceEnable Start/Stop Control Register, ETMTSSCR
2.3.7. TraceEnable Control Register 1, ETMTECR1
2.3.8. Address Comparator registers
2.3.9. Counter registers
2.3.10. Synchronization Frequency Register, ETMSYNCFR
2.3.11. ID Register, ETMIDR
2.3.12. Configuration Code Extension Register, ETMCCER
2.3.13. Extended External Input Selection Register, ETMEXTINSELR
2.3.14. Auxiliary Control Register, ETMAUXCR
2.3.15. CoreSight Trace ID Register, ETMTRACEIDR
2.3.16. Device Power-Down Status Register, ETMPDSR
2.3.17. OS Lock Status Register, OSLSR
2.3.18. Integration registers
2.3.19. Integration Mode Control Register, ETMITCTRL
2.3.20. Peripheral Identification registers
2.3.21. Component Identification registers
2.4. Event definitions
2.5. Implementation-defined behavior
2.6. Turning off the PTM-A9
2.7. Interaction with the performance monitoring unit
2.7.1. Use of PMU events by the PTM-A9
A. Signal Descriptions
A.1. PTM-A9 signal descriptions
A.1.1. Clocks and resets
A.1.2. ASIC level signals
A.1.3. Other signals
A.1.4. APB interface signals
A.1.5. ATB interface signals
A.1.6. Waypoint signals
Glossary

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A11 April 2008First release for r0p0
Copyright © 2008 ARM Limited. All rights reserved.ARM DDI 0401A
Non-Confidential