CoreSight™ PTM-A9 Technical Reference Manual

Revision: r1p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the PTM
1.1.1. PTM components
1.1.2. The CoreSight debug environment
1.2. PTM configuration
1.3. PTM components
1.3.1. Processor input FIFO
1.3.2. Trace blocks
1.3.3. Main FIFO
1.3.4. Clock domains
1.3.5. Level shifters
1.3.6. Cross-Trigger Interface
1.4. Prohibited regions for trace
1.5. Reset behavior
1.6. Product documentation, design flow, and architecture
1.6.1. Documentation
1.6.2. Design flow
1.6.3. Architecture information
1.7. Product revisions
2. Programmers Model
2.1. About this programmers model
2.2. Modes of operation
2.2.1. Using the Programming bit
2.2.2. Programming registers
2.3. Register short names
2.4. Register summary
2.5. Register descriptions
2.5.1. Main Control Register
2.5.2. Configuration Code Register
2.5.3. Status Register
2.5.4. System Configuration Register
2.5.5. TraceEnable Control registers
2.5.6. Address Comparator registers
2.5.7. Counter registers
2.5.8. Synchronization Frequency Register
2.5.9. ID Register
2.5.10. Configuration Code Extension Register
2.5.11. Extended External Input Selection Register
2.5.12. Auxiliary Control Register
2.5.13. CoreSight Trace ID Register
2.5.14. OS Lock Status Register
2.5.15. Device Power-Down Status Register
2.5.16. Integration registers
2.5.17. Integration Mode Control Register
2.5.18. Peripheral Identification registers
2.5.19. Component Identification registers
2.6. Event definitions
2.7. Implementation-defined behavior
2.8. Turning off the PTM
2.9. Interaction with the performance monitoring unit
2.9.1. Use of PMU events by the PTM
A. Signal Descriptions
A.1. PTM signal descriptions
A.1.1. Clocks and resets
A.1.2. ASIC level signals
A.1.3. Other signals
A.1.4. APB interface signals
A.1.5. ATB interface signals
A.1.6. Waypoint signals
B. Revisions

Proprietary Notice

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A11 April 2008First release for r0p0
Revision B31 December 2008First release for r1p0
Revision C08 July 2011Update for r1p0
Copyright © 2008-2011, ARM. All rights reserved.ARM DDI 0401C