2.1.1.  MBIST controller interface

The MBIST controller has one MBIST port, see Appendix A Signal Descriptions. Only one RAM is accessed by the MBIST controller at any time.

The MBIST controller must be able to account for the different latencies of the RAMs. You can configure RAM latencies for the cache controller RAMs. You can configure the Tag and Data RAMs for the following latencies:

See also Compiled RAM latencies.

You can use the MBIST controller for testing the cache controller compiled RAMs. You can also choose to design your own MBIST controller. You can only access one RAM by the MBIST port at a time.

Note

For the MBIST to run correctly on the cache controller, set the signals on the cache controller interface as follows:

  • set ASSOCIATIVITY to the relevant value for your design

  • set DATAWAIT, DATAERR, TAGWAIT, and TAGERR to 0

  • set the AXI ports to 0.

Figure 2.1 shows the interfaces between the MBIST controller and the RAMs that MBIST tests.

Figure 2.1. Cache controller MBIST and RAM interfaces


This section describes RAM latencies and the two MBIST RAM tests:

Compiled RAM latencies

The cache controller resets assuming the slowest compiled RAMs are being used. This means sixteen cache controller clock cycles are used for each access. In terms of reads, this means that the read data is sampled eight clock edges after the edge on which the read request is sampled by the RAM. Using this nomenclature, the shortest latency is one. During functional mode, the latencies for each RAM are programmed in the cache controller Auxiliary Control Register. For MBIST, you must know the latencies of the RAMs being tested. The MBIST controller defaults to one cycle of latency, but must reprogram this during the instruction load before MBIST testing can begin. The latency of the current RAM being tested is passed to the MBIST controller in the MBIST instruction. Table 2.1 shows the cache controller compiled RAM latency.

Table 2.1. Cache controller compiled RAM latency

Latency bits [3:0]Cycles of latency
4’b00001 cycle of latency. No additional latency. This is the default.
4’b00012 cycles of latency.
4’b00103 cycles of latency.
4’b00114 cycles of latency.
4’b01005 cycles of latency.
4’b01016 cycles of latency.
4’b01107 cycles of latency.
4’b01118 cycles of latency.
4’b10009 cycles of latency.
4’b100110 cycles of latency.
4’b101011 cycles of latency.
4’b101112 cycles of latency.
4’b110013 cycles of latency.
4’b110114 cycles of latency.
4’b111015 cycles of latency.
4’b111116 cycles of latency.

Figure 2.2 shows the cache controller compiled RAM latency.

Figure 2.2. Cache controller compiled RAM latency


MBIST testing of cache controller data RAM

The cache controller data RAM is 256 bits wide, and the size of the MBISTDIN and MBISTDOUT buses on the cache controller MBIST interface is 64 bits, so four reads and four writes are required for each index of the data RAM. The cache controller handles this by using the MBISTADDR[1:0] signal as a doubleword select for each index of the data RAM for writes. For reads from a previous MBIST transaction you use the MBISTDCTL[1:0] signal. You require separate pins because the MBIST transactions are pipelined. The MBIST controller takes into account the data RAM latency and issues the correct control signals. Table 2.2 shows the address range of the MBISTADDR bus used to test the data RAM, based on the L2 cache size and configured to be 8-way.

Table 2.2. MBISTADDR and MBISTDIN mapping for data RAM, 8-way

L2 cache sizeNumber of data RAM indexesMBISTADDR to data RAM mapping MBISTDIN to data RAM mapping
128KB4,096DATAADDR[11:0]=MBISTADDR[18:16,10:2]DATAWD[63:0]=MBISTDIN[63:0]
256KB8,192DATAADDR[12:0]=MBISTADDR[18:16,11:2]DATAWD[63:0]=MBISTDIN[63:0]
512KB16,384DATAADDR[13:0]=MBISTADDR[18:16,12:2]DATAWD[63:0]=MBISTDIN[63:0]
1MB32,768DATAADDR[14:0]=MBISTADDR[18:16,13:2]DATAWD[63:0]=MBISTDIN[63:0]
2MB65,536DATAADDR[15:0]=MBISTADDR[18:16,14:2]DATAWD[63:0]=MBISTDIN[63:0]
4MB131,072DATAADDR[16:0]=MBISTADDR[18:2]DATAWD[63:0]=MBISTDIN[63:0]

For a 16-way cache, you can remove one bit from the lower address range and add it to the upper address range as compared to an 8-way cache of the same size. Table 2-3 shows the address range of the MBISTADDR bus used to test the data RAM, based on the L2 cache size and configured to be 16-way.

Table 2.3. MBISTADDR and MBISTDIN mapping for data RAM, 16-way

L2 cache sizeNumber of data RAM indexesMBISTADDR to data RAM mappingMBISTDIN to data RAM mapping
256KB8,192DATAADDR[12:0]=MBISTADDR[19:16,10:2]DATAWD[63:0]=MBISTDIN[63:0]
512KB16,384DATAADDR[13:0]=MBISTADDR[19:16,11:2]DATAWD[63:0]=MBISTDIN[63:0]
1MB32,768DATAADDR[14:0]=MBISTADDR[19:16,12:2]DATAWD[63:0]=MBISTDIN[63:0]
2MB65,536DATAADDR[15:0]=MBISTADDR[19:16,13:2]DATAWD[63:0]=MBISTDIN[63:0]
4MB131,072DATAADDR[16:0]=MBISTADDR[19:16,14:2]DATAWD[63:0]=MBISTDIN[63:0]
8MB262,144DATAADDR[17:0]=MBISTADDR[19:2]DATAWD[63:0]=MBISTDIN[63:0]

The cache controller has a 256-bit wide Line Read Buffer (LRB) in each slave. One of these holds data for MBIST testing. The cache controller always adds two register delays to the MBIST data read path for the data RAM.

When using the MBIST controller you must account for the data RAM latency in the pipeline. The latency can be from one to eight clock cycles. See Compiled RAM latencies. The signal MBISTCE[0] is for the chip enable to the data RAM. The signal MBISTDCTL[2:0] is for reads from previous MBIST transactions.

Figure 2.3 shows the cache controller MBIST paths for data RAM testing.

Figure 2.3. Cache controller MBIST paths for data RAM testing


Table 2.4 shows the write sequences for data RAM testing.

Table 2.4. Writes for data RAM testing

MBISTADDR[1:0]DATAEN[31:0]DATAWD used
b000x000F[63:0]
b010x00F0[127:64]
b100x0F00[191:128]
b110xF000[255:192]

MBIST testing of cache controller tag RAMs

There is one tag RAM for each way of the L2 cache. The maximum number of tag RAMs the MBIST controller has to test is 16. Only one tag RAM is tested at a time. Table 2.5 shows the address range of the MBISTADDR bus used to test a tag RAM, based on the L2 cache size and configured to be 8-way. The parity for each tag RAM present is tested along with the rest of the tag and is mapped to MBISTDIN[22]. Lockdown by line is tested with the rest of the tag and is mapped to MBISTDIN[21].

Table 2.5. MBISTADDR and MBISTDIN mapping for tag RAM, 8-way

L2 cache sizeWay sizeNumber of tag RAM indexesMBISTADDR to tag RAM mappingMBISTDIN to tag RAM mapping
128KB16KB512TAGADDR[8:0]=MBISTADDR[10:2]TAGWD[20:0]=MBISTDIN[20:0]
256KB32KB1,024TAGADDR[9:0]=MBISTADDR[11:2]TAGWD[20:1]=MBISTDIN[20:1]
512KB64KB2,048TAGADDR[10:0]=MBISTADDR[12:2]TAGWD[20:2]=MBISTDIN[20:2]
1MB128KB4,096TAGADDR[11:0]=MBISTADDR[13:2]TAGWD[20:3]=MBISTDIN[20:3]
2MB256KB8,192TAGADDR[12:0]=MBISTADDR[14:2]TAGWD[20:4]=MBISTDIN[20:4]
4MB512KB16,384TAGADDR[13:0]=MBISTADDR[15:2]TAGWD[20:5]=MBISTDIN[20:5]

For all cases:

  • lockdown by line TAGLWD=MBISTDIN[21]

  • parity TAGPWD=MBISTDIN[22].

Table 2.6 shows the address range of the MBISTADDR bus used to test the tag RAM, based on the L2 cache size and configured to be 16-way.

Table 2.6. MBISTADDR and MBISTDIN mapping for tag RAM, 16-way

L2 cache sizeWay sizeNumber of tag RAM indexes MBISTADDR to tag RAM mapping MBISTDIN to tag RAM mapping
256KB16KB512TAGADDR[8:0]=MBISTADDR[10:2]TAGWD[20:0]=MBISTDIN[20:0]
512KB32KB1,024TAGADDR[9:0]=MBISTADDR[11:2]TAGWD[20:1]=MBISTDIN[20:1]
1MB64KB2,048TAGADDR[10:0]=MBISTADDR[12:2]TAGWD[20:2]=MBISTDIN[20:2]
2MB128KB4,096TAGADDR[11:0]=MBISTADDR[13:2]TAGWD[20:3]=MBISTDIN[20:3]
4MB256KB8,192TAGADDR[12:0]=MBISTADDR[14:2]TAGWD[20:4]=MBISTDIN[20:4]
8MB512KB16,384TAGADDR[13:0]=MBISTADDR[15:2]TAGWD[20:5]=MBISTDIN[20:5]

The data from the tag RAMs is always registered by the cache controller. There is a register on the MBIST port of the cache controller. Consequently, to the MBIST controller, the cache controller always adds two register delays to the MBIST data read path for the tag RAMs.

When using the MBIST controller you must account for the Tag RAM latency in the pipeline. The signal MBISTCE[16:1] is for chip enables to the tag RAMs. The signal MBISTDCTL[18:3] is for reads from previous MBIST transactions. The latency of the tag RAMs can be from one to eight clock cycles. See Compiled RAM latencies.

Figure 2.4 shows the cache controller MBIST paths for tag RAM testing.

Figure 2.4. Cache controller MBIST paths for tag RAM testing


Note

  • MBISTCE[16:1] corresponds to TAGCS[15:0]

  • MDBISTDCL[18:3] corresponds to TAG[15:0]

  • Only bits [22:0] of MBISTDIN and MBISTDOUT are used.

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