1.1. About the MBIST controller

MBIST is the industry-standard method of testing embedded memories. MBIST works by performing sequences of reads and writes to the memory according to a test algorithm. Many industry-standard test algorithms exist.

An MBIST controller generates the correct sequence of reads and writes to all locations of the RAM to ensure that the cells are operating correctly. In doing this, some additional test coverage is achieved in the address and data paths that the MBIST uses. You must only use the MBIST controller with the cache controller to perform memory testing of the Level 2 (L2) cache RAM.

Note

The example integration files provided with the MBIST controller only support a 16-way cache design.

MBIST mode takes priority over all other modes, for example scan testing, in that the L2 RAMs are only accessible to the MBIST controller when MBIST mode is activated with the MTESTON pin. You must keep the MTESTON signal LOW during functional mode, and the AXI interfaces LOW during MBIST mode.

The MBIST controller controls the MBIST testing of the L2 RAMs through the MBIST port of the cache controller. Figure 1.1 shows the cache controller MBIST configuration.

When MTESTON is HIGH, the MBIST block, the cache controller, and the RAMs must be clocked at the same frequency.

Figure 1.1. Cache controller MBIST configuration without data banking


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