A.1. MBIST controller interface signals

Table A.1 shows the MBIST controller interface signals.

Table A.1. MBIST controller interface signals

SignalTypeDescription
MBISTDOUT[63:0]Input

MBIST data out, from cache controller

MBISTDOUT[63:0] = MBIST data out for Data RAM

MBISTDOUT[20:0] = MBIST data out for Tag RAM

MBISTADDR[19:0]Output

MBIST address

MBISTADDR[18:0] used for Data RAM, two LSBs used as doubleword select

MBISTADDR[14:2] used for Tag RAM

MBISTCE[17:0]Output

MBIST RAM chip enables, for writes

MBISTCE[0] = Data RAM chip enable

MBISTCE[1] = Tag RAM 0 chip enable

MBISTCE[2] = Tag RAM 1 chip enable

MBISTCE[3] = Tag RAM 2 chip enable

MBISTCE[4] = Tag RAM 3 chip enable

MBISTCE[5] = Tag RAM 4 chip enable

MBISTCE[6] = Tag RAM 5 chip enable

MBISTCE[7] = Tag RAM 6 chip enable

MBISTCE[8] = Tag RAM 7 chip enable

MBISTCE[9] = Tag RAM 8 chip enable

MBISTCE[10] = Tag RAM 9 chip enable

MBISTCE[11] = Tag RAM 10 chip enable

MBISTCE[12] = Tag RAM 11 chip enable

MBISTCE[13] = Tag RAM 12 chip enable

MBISTCE[14] = Tag RAM 13 chip enable

MBISTCE[15] = Tag RAM 14 chip enable

MBISTCE[16] = Tag RAM 15 chip enable

MBISTCE[17] = Data parity chip enable[a]

MBISTDCTL[19:0]Output

MBIST control, for reads

MBISTDCTL[1:0] = MBIST data select for 64 bits of 256 wide data RAM

MBISTDCTL[2] = MBIST RAM select for Data RAM

MBISTDCTL[3] = MBIST RAM select for Tag RAM 0

MBISTDCTL[4] = MBIST RAM select for Tag RAM 1

MBISTDCTL[5] = MBIST RAM select for Tag RAM 2

MBISTDCTL[6] = MBIST RAM select for Tag RAM 3

MBISTDCTL[7] = MBIST RAM select for Tag RAM 4

MBISTDCTL[8] = MBIST RAM select for Tag RAM 5

MBISTDCTL[9] = MBIST RAM select for Tag RAM 6

MBISTDCTL[10] = MBIST RAM select for Tag RAM 7

MBISTDCTL[11] = MBIST RAM select for Tag RAM 8

MBISTDCTL[12] = MBIST RAM select for Tag RAM 9

MBISTDCTL[13] = MBIST RAM select for Tag RAM 10

MBISTDCTL[14] = MBIST RAM select for Tag RAM 11

MBISTDCTL[15] = MBIST RAM select for Tag RAM 12

MBISTDCTL[16] = MBIST RAM select for Tag RAM 13

MBISTDCTL[17] = MBIST RAM select for Tag RAM 14

MBISTDCTL[18] = MBIST RAM select for Tag RAM 15

MBISTDCTL[19] = MBIST RAM select for data parity

MBISTDIN[63:0]Output

MBIST Data In, to cache controller

MBISTDIN[63:0] = MBIST data in for Data RAM

MBISTDIN[20:0] = MBIST data in for Tag RAM

MBISTWE[31:0]OutputMBIST Write enable

[a] Data parity enable is MBISTCE[17] on the MBIST controller. However, the cache controller interface is configurable as 16-way or 8-way. For a16-way configuration, connect MBISTCE[17] from the MBIST controller to MBISTCE[17] on the cache controller. For an 8-way configuration, connect MBISTCE[17] from the MBIST controller to MBISTCE[9] on the cache controller.


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