3.2.4. Y-address and X-address fields, MBIR[36:33] and MBIR[40:37]

You can determine the number of address bits you must specify for a RAM from the MBIR fields:

This enables you to specify your address range in two dimensions, this represents the topology of the physical implementation of the RAM more accurately. These two dimensions are controlled by two separate address counters, the X-address counter and the y-address counter. One counter can be incremented or decremented only when the other counter has expired. The chosen test algorithm determines the counter that moves faster.

Normal mode

Use this procedure to determine how many bits to assign to the X-address and Y-address counters:

  1. Determine the column width of the RAM array. The Y-address must have at least that many bits for the column select. If it is a Data RAM, add two bits to that number for the doubleword select.

  2. Determine how many address bits the RAM requires. See Cache controller RAMs. Subtract the current Y-address bit number from that number. If the result is eight or fewer bits, they are all assigned to the X-address for the row select. Otherwise, eight bits are used for the X-address and any unassigned bits are added to the bits already assigned to the Y-address and used for the block select.

Figure 3.2 shows an example topology for the Data RAM in a 256K level-2 cache.

Figure 3.2. Example data RAM topology


The cache RAM in Figure 3.2 has a column width of 16, so it uses four bits for the column address. These four bits map to the least significant bits of the Y-address counter. Because this is a data RAM, it requires two additional doubleword select bits. The doubleword select bits choose between the four 64-bit groups of RAM data before sending the data to the 64-bit MBISTDOUT[63:0] bus. These two bits always map to the Y-address counter bits between the column address and the block address.

Because this cache RAM has 256 rows per column, it uses eight bits for the row address, this uses up all eight bits of the X-address counter. This RAM also contains two blocks of 16 columns each, so it uses one bit for the block address. This maps to the most significant bit of the Y-address counter. To correctly test this RAM, the Y-address field must have a value of seven, MBIR[36:33] = b0111, and the X-address field must have a value of eight, MBIR[40:37] = b1000. Values higher or lower than these produce incorrect results.

Note

If the columns have fewer than 256 rows, you must still assign address bits to the row address until all eight bits are used before assigning any to the block address. If the cache RAM has more than 256 rows per column, then the additional bits must be assigned to the block address. This does not have any detrimental effects on the test coverage of the RAM.

Figure 3.3 shows how the MBIST controller builds the address output. The doubleword select bits are the least significant two bits of the address. These two bits are ignored unless the data RAM is selected. The exclusive OR of the two least significant bits of the Y-address counter is the least significant bit of the column address for physical addressing of the columns. This is followed by the row address from the X-address counter and, if required, the block address.

Figure 3.3. MBIST address scrambling for normal mode


Banked RAM organization

The X-address field for banked RAM is determined the same way as in normal RAM mode. For both data RAM and data parity RAM, the Y-address field is same as in normal RAM mode but with the addition of two bits to select the RAM bank.

Tag RAM address mapping for banked RAM is the same as non-banked RAM. See Figure 3.3.

Figure 3.4 shows the structure for banked mode data RAM and banked mode data parity RAM.The only difference from normal mode RAM is that two of the Y-address counter bits now form the Bank select.

Figure 3.4. MBIST address scrambling for banked mode data and data parity ram


Y-address

The Y-address field specifies the number of Y-address counter bits to use during test. Table 3.6 shows the Y-address settings.

Table 3.6. Y-address field encoding

Y-address MBIR[36:33]Number of counter bits
<b0010Unsupported
b00102
b00113
b01004
b01015
b01106
b01117
b10008
b10019
b101010
>b1010Reserved

X-address

The X-address field specifies the number of X-address counter bits to use during test. Table 3.7 shows the X address settings.

Table 3.7. X-address field encoding

X-address MBIR[40:37]Number of counter bits
<b0010Unsupported
b00102
b00113
b01004
b01015
b01106
b01117
b10008
b10019
b101010
>b1010Reserved

Cache controller RAMs

Table 3.8 shows the required sums of the X-address and Y-address fields for testing of data RAM.

Table 3.8. Required sums of X-address and Y-address fields for data RAM

Cache sizeData RAM
128KB14
256KB15
512KB16
1MB17
2MB18
4MB19
8MB20

Table 3.9 shows the required sums of the X-address and Y-address fields for testing of tag RAM.

Table 3.9. Required sums of X-address and Y-address fields for tag RAM

Way sizeTag RAM
16KB9
32KB10
64KB11
128KB12
256KB13
512KB14

Table 3.10 shows the required sums of the X-address and Y-address fields for testing of data parity RAM.

Table 3.10. Required sums of X-address and Y-address fields for data parity RAM

Cache sizeData parity RAM
128KB12
256KB13
512KB14
1MB15
2MB16
4MB17
8MB18

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